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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15720完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 汪重光(Chorng-Kuang Wang) | |
| dc.contributor.author | Keng-Yu Lin | en |
| dc.contributor.author | 林耿裕 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:50:43Z | - |
| dc.date.copyright | 2013-01-16 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-11-26 | |
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Svelto, “A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques,” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 824-834, Mar. 2009. [32] C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, “A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 344-618, Feb. 2008. [33] R. B. Staszewski and P. T. Balsara, “Phase-Domain All-Digital Phase-Locked Loop,” IEEE Transactions on Circuits and Systems II, vol. 52, no. 3, pp. 159-163, Mar. 2005. [34] R. B. Staszewski, C. M. Hung, K. Maggio, J. Wallberg, D. Leipold, and P. T. Balsara, “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13μm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 272-273, Feb. 2004. [35] R. B. Staszewski, D. Leipold, C. M. Hung, and P. T. Balsara, “TDC-Based Frequency Synthesizer for Wireless Applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 215-218, Jun. 2004. [36] R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 3, pp. 220-224, Mar. 2006. [37] R. B. Staszewski et al., “All-Digital PLL and Transmitter for Mobile Phones,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2469-2481, Dec. 2005. [38] R. Srinivasan, D. Z. Turker, S. W. Park, and E. S. Sinencio, “A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications,” IEEE International Symposium on Circuit and Systems, pp.429-432, May 2007. [39] Y. C. Chuang, 'An All-Digital Phase-Locked with Dynamic Phase Control for Fast Locking,' in Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, May 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15720 | - |
| dc.description.abstract | 由於科技的不斷進步，元件尺寸及功率消耗持續地在下降，在單一晶片中，越來越多的功能區塊被包含進去，然而，隨著製程的演進，不理想的效應也伴隨著出現。類比元件面臨著元件特性的衰退，像是供給電壓的下降、漏電流的增加等等，因此，使用數位電路取代類比電路已成了一種趨勢。
2.4-GHz工業、科學以及醫療(ISM)頻帶被許多短距離無線通訊系統所使用，像是WLAN、Bluetooth以及Zigbee。近年來，鎖相迴路被廣泛地應用在有線及無線通訊系統之中，如同上述所提到的，全數位鎖相迴路更適合應用在先進的製程之中。因此，本論文提出一種使用低功率時間數位轉換器的全數位鎖相迴路。 在論文的一開始，會先分析此設計，並提出相對應的模型，緊接著會介紹電路如何實現。最後，本設計使用台積電0.18微米製程製造，而時間數位轉換器省下了66%的功率消耗。量測到的相位雜訊在1 MHz及10 MHz的頻率偏移下分別為-114 dBc/Hz和-118 dBc/Hz，量測到的均方根時脈抖動為0.64 ps。在1.8 V的供給電壓下量測到的功率消耗為14.1 mW。 | zh_TW |
| dc.description.abstract | Due to the progress in technology, device size and power consumption keep scaling down. Moreover, more and more function blocks are integrated in a single chip. However, there are also some non-ideal effects accompanied with the progressing CMOS technology. Analog devices suffer from the degrading characteristic such as decreasing supply voltage and increasing leakage current. Thus, it is a tendency that using digital circuits to replace analog circuits.
The 2.4-GHz industrial, scientific and medical (ISM) band is utilized by various short-range wireless systems such as WLAN, Bluetooth and Zigbee. Recently, phase-locked loops (PLLs) are widely used in wireless and wireline communication. As mentioned above, all-digital phase-locked loops (ADPLLs) are more suitable for advanced technology. Thus, this thesis presents an all-digital phase-locked loop with low power time-to-digital (TDC) converter. The design is analyzed and modeled first, than the implantation is presented. Finally, the chip is fabricated in the TSMC 0.18 μm CMOS technology. The power consumption of TDC is reduced 66%. The measured phase noise are -114 dBc/Hz and -118 dBc/Hz at 1 MHz and 10 MHz offset, respectively and the rms jitter is 0.64 ps. The power consumption is 14.1 mW from 1.8 V supply voltage. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:50:43Z (GMT). No. of bitstreams: 1 ntu-101-R98943031-1.pdf: 2159098 bytes, checksum: 75cc422907792e2a4927622476b8d3df (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES ix LIST OF TABLES xiii Chapter 1 Introduction 1 1.1 Introduction of All-Digital Phase-Locked Loops (ADPLLs) 1 1.1.1 Time-to-Digital Converter (TDC) 1 1.1.2 Digital Loop Filter (DLF) 3 1.1.3 Digital-Controlled Oscillator (DCO) 4 1.1.4 Divider 5 1.1.5 Summary 6 1.2 Motivation 7 1.3 Overview of this thesis 7 Chapter 2 Proposed ADPLL with Low Power Time-to Digital Converter Design 9 2.1 Principle of the Proposed Architecture 9 2.1.1 Background 9 2.1.2 Gated-Ring Oscillator based Time-to-Digital Converter 11 2.1.3 Proposed Low Power Time-to-Digital Converter 12 2.2 Linear Model Analysis of Proposed ADPLL 14 2.2.1 Coarse-tune mode 14 2.2.2 Fine-tune mode 15 2.2.3 Stability Analysis 16 2.2.4 Hold range and Lock range 18 2.2.5 Phase Noise and Jitter 20 2.2.6 Design Flow and Behavior System Simulation 24 2.3 Circuit Implementations 28 2.3.1 Time-to-Digital Converter 28 2.3.2 Digital Controlled Oscillator 35 2.3.3 Digital Loop Filter 38 2.3.4 Summary 40 Chapter 3 Experimental Results 41 3.1 Test Setup 41 3.2 Experimental Results 43 3.3 Summary 49 Chapter 4 Conclusions 53 REFERENCE 55 | |
| dc.language.iso | en | |
| dc.subject | 時間數位轉換器 | zh_TW |
| dc.subject | 全數位鎖相迴路 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | Low Power | en |
| dc.subject | TDC | en |
| dc.subject | All digital phase locked loop | en |
| dc.title | 應用於Zigbee之低功率全數位鎖相迴路設計 | zh_TW |
| dc.title | Design of All-Digital Phase-Locked Loop with Low Power Time-to-Digital Converter for Zigbee Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,林宗賢,郭泰豪,黃柏鈞 | |
| dc.subject.keyword | 全數位鎖相迴路,低功率,時間數位轉換器, | zh_TW |
| dc.subject.keyword | All digital phase locked loop,Low Power,TDC, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2012-11-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-101-1.pdf 未授權公開取用 | 2.11 MB | Adobe PDF |
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