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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15595完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Ko-Wen Liao | en |
| dc.contributor.author | 廖可文 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:48:27Z | - |
| dc.date.copyright | 2013-03-15 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-02-18 | |
| dc.identifier.citation | [1] Y. Tomita, M. Kibune, J. Ogawa, W.W. Walker, H. Tamura, and T. Kuroda, “A 10-Gb/s Receiver With Series Equalizer and On-Chip ISI Monitor in 0.11-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 986–993, Apr. 2005.
[2] D. Lee, J. Han, G. Han, and S.M. Park, “10 Gbit/s 0.0065 mm2 6mW Analogue Adaptive Equaliser Utilising Negative Capacitance”, Electronics Letters, vol. 45, no. 17, pp. 863-865, Aug. 2009. [3] J. Lee, “A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS TEchnology,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2058–2066, Sep. 2006. [4] S. Shahramian, C. Ting, A. Shelkholeslami, H. Tamura, and M. Kibune, “A Pattern-Guided Adaptive Equalizer in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 354–355. [5] W.-S. Kim, C.-K. Seong, and W.-Y. Choi, “A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 358–359. [6] Y.-M. Ying and S.-I. Liu, “A 20Gb/s Digitally Adaptive Equalizer/DFE with Blind Sampling,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 444–445. [7] K. Yamaguichi, K. Sunaga, S. Kaeriyama, T. Nedachi, M. Takamiya, K. Nose, Y. Nakagawa, M. Sugawara, and M. Fukaishi, “12Gb/s Duobinary Signaling with 2 Oversampled Edge Equalization,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 70–71. [8] J. Lee, M.-S. Chen, and H.-D. Wang, “Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4 and NRZ Data,” IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2120–2133, Sep. 2008. [9] A. Momtaz and M. M. Green, “An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 629–639, Mar. 2010. [10] R. Payne, P. Landman, B. Bhakta, S, Ramaswamy, S. Wu, J. D. Powers, M. U. Erdogan, A.-L. Lee, R. Gu, L. Wu, Y. Xie, B. Parthasarathy, K. Brouse, W. Mohammed, K. Heragu, V. Gupta, L. Dyson, and W. Lee, “A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2646–2657, Dec. 2005. [11] M. Pozzoni, S. Erba, P. Viola, M. Pisati, E. Depaoli, D. Sanzogni, R. Brama, D. Baldi, M. Repossi, and F. Svelto, “A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1306–1315, Apr. 2009. [12] K. Sunaga, H. Sugita, K. Yamaguchi, and K. Suzuki, “An 18Gb/s Duobinary Receiver with a CDR-Assisted DFE,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 274–275. [13] Y.-M. Ying, “The Equalizers with Adaptive Techniques in High-Speed Backplane Communication,” M.S. thesis, Graduate Institute of Electronics Engineering, National Taiwan Univ., Taipei, Taiwan, 2011. [14] R.inti, W. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, “A 0.5-to-2.5 Gbs Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3150–3162, Dec. 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15595 | - |
| dc.description.abstract | 近十年來，人們對於各種有線傳輸技術的興趣日趨濃厚。有線傳輸的其中一項應用就是晶片與晶片間的傳輸。為了要能使製造成本降低，各個晶片的輸入輸出通道數目，這就造成每個輸入輸出通道的傳輸速度必須提高。傳輸速度的提高會使得資料在通道中傳輸時候到更大的衰減，一個可適性等化器可以用來補償這些衰減，並且可以針對不同的通道作自動調整。另一種減少通道衰減的方法是使用不同的訊號形式，某些訊號形式可以藉由受到較小的衰減的特性提升訊號的完整度。
本論文主要分為兩個部分，在第二章中提出了兩個非同步取樣之可適性等化器，並且分別實現了兩個可以快速收斂的演算法。第一個方法偵測波形的大小，補償完成後在波峰以及連續相同資料時的訊號大小應相同，這個電路使用40奈米CMOS製程作實現，操作速度為8 Gb/s，它可以補償16.4dB的衰減，補償完的錯誤率小於10-12，量測到的收斂時間分別是450ns，消耗的功率分別為85.5mW。而第二個方法是計算訊號轉換的次數，補償完成後累積特定次數的時間應是一個定值，這些電路同樣是使用40奈米CMOS製程作實現且操作速度為8 Gb/s，它也可以補償16.4dB的衰減，補償完的錯誤率小於10-12，量測到的收斂時間是2700ns消耗的功率為17.6mW。 在第三章中，提出了一個雙二元之可適性收發器。這個收發器包含了傳輸端與接收端的等化器以及一個補償調整電路。除此之外，也提出了一個可以適用於這種訊號形式的演算法。這個收發器是使用40奈米CMOS製程來做實現，而且可以操作在18 Gb/s，最大可以補償14.7dB 的衰減，補償完的錯誤率小於10-12，量測結果顯示傳輸端消耗的功率為65mW，接收端中等化器消耗了55mW，而補償調整電路消耗了85mW。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:48:27Z (GMT). No. of bitstreams: 1 ntu-102-R99943038-1.pdf: 3854158 bytes, checksum: 6ddc30f4302da4248ee562436771f03b (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 1. Introduction………………………………………………………… 1
1.1 Wireline Communications………………………………........ 2 1.2 Adaptive Linear Equalizers with Blind Sampling………….... 3 1.3 Adaptive Duobinary Transceivers…………………………… 6 1.4 Objective of the Thesis………………………………………. 8 1.5 Content of the Thesis………………………………………… 8 2. Two 8Gb/s Fast-Locking Adaptive Linear Equalizers with Blind Sampling…………………………………………………………….. 9 2.1 Adaptive Equalizer by Amplitude Detection………………… 10 2.1.1 The Adaptation Algorithm…………..……………….. 10 2.1.2 System Architecture………………………………….. 12 2.1.3 Circuit Design………………………………………... 18 2.2 Adaptive Equalizer by Edge Counting………………………. 24 2.2.1 The Adaptation Algorithm…………………………… 24 2.2.2 System Architecture………………………………….. 26 2.2.3 Circuit Design……...………………………………… 30 2.3 Experimental Results………………………………………… 35 2.3.1 Adaptive Equalizer by Amplitude Detection………… 35 2.3.2 Adaptive Equalizer by Edge Counting………………. 40 2.4 Conclusion…………………………………………………… 50 3. An 18 Gb/s Adaptive Duobinary Transceiver…………………….. 51 3.1 The Adaptation Algorithm……………... 52 3.2 System Architecture and Circuit Description 56 3.2.1 System Architecture 56 3.2.2 Transmitter-Side FFE………………………………... 57 3.2.3 Merged DFE…………………………………………. 57 3.2.4 Adaptation Circuit…………………… 59 3.3 Experimental Results……………………..…………………. 63 3.4 Conclusion…………………………………………………… 73 4. Conclusions and Future Works………….……………………….... 75 4.1 Conclusions..………………………………………………… 76 4.2 Future Works..……………………………………………….. 76 Bibliography ……………………………………………………………….. 79 | |
| dc.language.iso | en | |
| dc.title | 快速鎖定之非同步取樣可適性等化器及一個雙二元收發器 | zh_TW |
| dc.title | Fast-Locking Adaptive Equalizers with Blind Sampling and A Duobinary Transceiver | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),汪重光(Chorng-Kuang Wang),楊清淵(Ching-Yuan Yang),郭泰豪(Tai-Haur Kuo) | |
| dc.subject.keyword | 等化器,快鎖,可適性,隨機取樣,雙二元,收發器, | zh_TW |
| dc.subject.keyword | equalizer,fast-locking,adaptive,blind,sampling,duobinary,transceiver, | en |
| dc.relation.page | 81 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2013-02-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-102-1.pdf 目前未授權公開取用 | 3.76 MB | Adobe PDF |
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