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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15466完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉深淵(Shen-Iuan Liu) | |
| dc.contributor.author | Yen-Min Tseng | en |
| dc.contributor.author | 曾彥閔 | zh_TW |
| dc.date.accessioned | 2021-06-07T17:40:52Z | - |
| dc.date.copyright | 2020-07-22 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-07-20 | |
| dc.identifier.citation | [1] E. Alon, J. Kim, S. Pamarti, K Chang, and M. Horowitz, “Replica compensated linear regulators for supply-regulated phase-locked loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006. [2] T. Wu, K. Mayaram, and U.-K. Moon, “An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007. [3] S. Y. Kao, and S. I. Liu, “A digitally-calibrated phase-locked loop with supply sensitivity suppression,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 19, no. 4, pp. 592-602, Apr. 2011. [4] Y. C. Huang, C. F. Liang, H. S. Huang, and P. Y. Wang, “A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 270-271, Feb. 2014. [5] A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2759–2771, Dec. 2011. [6] J. Liu, T. K. Jang, Y. Lee, J. Shin, S. Lee, T. Kim, J. Park, and H. Park, “A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 268-269, Feb. 2014. [7] C. W. Yeh, C. E. Hsieh, and S. I. Liu, “A 3.2GHz digital phase-locked loop with background supply-noise cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2016. [8] Y. Okuma, et al. “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS,” IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, Sept. 2010. [9] T. Jang, S. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, “A noise reconfigurable all-digital phase-locked Loop using a switched capacitor-based frequency-locked loop and a noise detector,” IEEE J. Solid-State Circuits, vol. 53, no. 1, pp. 50–65, Jan. 2018. [10] C. W. Tien, and S. I. Liu, “A digital phase-locked loop with background supply voltage sensitivity minimization,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 6, pp. 1830–1839, June 2018. [11] Y. C. Huang, C. F. Liang, H. S. Huang, and P. Y. Wang, “A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO,' in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 270-271, Feb. 2014. [12] B. Razavi, “The StrongARM latch [A circuit for all seasons],” IEEE Solid-State Circuits Mag., vol. 7, no. 2, pp. 12-17, Spring 2015. [13] P. H. Hsieh, J. Maxey, and C. K. K. Yang, “Minimizing the supply sensitivity of a CMOS ring oscillator through jointly biasing the supply and control voltages,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2488-2495, Sep. 2009. [14] Y. C. Huang and S. I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Apr. 2013. [15] I. T. Lee, et al. “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 414-415, Feb. 2013. [16] A. Li, et al. “A spur-and-phase-noise-filtering technique for inductor-less fractional-N injection-locked PLLs,” IEEE J. Solid-State Circuits, vol. 52, no. 8, pp. 2128–2140, Aug. 2017. [17] S. Levantino, et al. “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2678–2691, Nov. 2015. [18] H. Kim, et al. “A 2.4-GHz 1.5-mw digital multiplying delay-locked loop using pulsewidth comparator and double injection technique,” IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2934–2646, Nov. 2017. [19] A. Elshazly, R. Inti, B. Young, and P. K. Hanumolu, “Clock multiplication techniques using digital multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416–1428, Jun. 2013. [20] A. Elkholy, A. Elmallah, M. G. Ahmed, and P. K. Hanumolu, “A 6.75-8.25-GHz -250-dB FoM rapid on/off fractional-N injection-locked clock multiplier,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1818–1829, June 2018. [21] A. Elkholy, D. Coombs, R. K. Nandwana, A. Elmallah, and P. K. Hanumolu, “A2.5-5.75-GHz ring-based injection-locked clock multiplier with background-calibrated reference frequency doubler,” IEEE J. Solid-State Circuits, vol. 54, no. 7, pp. 2049–2058, July 2019. [22] S. Choi, S. Yoo, Y. Lim, and J. Choi, “A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878–1889, Aug. 2016. [23] S. Ye and I. Galton, “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, Dec. 2002. [24] B. Razavi, “A study of injection locking and pulling in oscillator,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004. [25] W. Deng, et. al., “A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2015. [26] C. L. Wei, T. K. Kuan and S. I. Liu, 'A sub-harmonically injection-locked PLL with calibrated injection pulse width', IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 62, pp. 548-552, June 2015. [27] J. Shin and H. Shin, “A fast and high-precision VCO frequency calibration technique for wideband ΣΔ fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582, July 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15466 | - |
| dc.description.abstract | 這篇論文的主題主要分為兩個部分，第一部分實現了一個具有背景消除供應電壓雜訊的數位鎖相迴路。藉由使用一個數位穩壓器以及全數位電壓源雜訊消除方法，此數位鎖相迴路可以承受峰對峰值為240mV的供應電壓源雜訊。此數位鎖相迴路使用台積電40奈米製程，面積為0.0195mm2 而功耗在1.1V的供應電壓下為7.23mW。數位振盪器量測到最小的電壓源雜訊敏感度低於0.0261[%-fDCO/%-VDD]。在供應電壓源注入峰對峰值為240mV，頻率為100kHz的弦波雜訊時，量測到的方均根抖動量從原本的56.38ps降低至15.72ps。 第二部分實現了一個具有注入強度校正的注入鎖定時脈倍頻器。通過控制電荷泵電流，可以使用注入強度校正器來校準注入鎖定時脈倍頻器的注入強度。此注入鎖定時脈倍頻器使用台積電40奈米製程，面積為0.0253mm2 而功耗在1V的供應電壓下為4.28mW。參考頻率為150MHz，輸出頻率為2.4GHz以及除數為16。相位噪聲積分範圍從1kHz到100MHz所量測到的方均根抖動量為878fs。 | zh_TW |
| dc.description.abstract | This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply noise cancellation. By using a digital low-dropout regulator and a supply noise cancellation controller, this DPLL can tolerate a supply noise of 240mVPP. The DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0195mm2 and the total power consumption is 7.23mW from a supply of 1.1V. The minimum measured supply voltage sensitivity of the digital-controlled oscillator is less than 0.0261 [%-fDCO/%-VDD]. With a 100kHz, 240mVPP sinusoidal supply noise, the measured rms jitter is reduced from 56.38ps to 15.72ps. The second part implements an injection-locked clock multiplier (ILCM) with injection strength calibration. By controlling the charge pump currents, an injection strength calibrator is used to calibrate the injection strength of the ILCM. This ILCM is fabricated in 40-nm CMOS technology. Its active area is 0.0253mm2. The power consumption of the ILCM is 4.28mW from a supply of 1V. The reference frequency is 150MHz and the output frequency is 2.4GHz with a divider ratio of 16. The measured rms jitter integrated the phase noise from 1kHz to 100MHz is 878fs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-07T17:40:52Z (GMT). No. of bitstreams: 1 U0001-2007202013514100.pdf: 2188947 bytes, checksum: 7f16e02b64d42796215a06224a0ca3f8 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 1. Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 2. A Digital Phase-Locked Loop With Background Supply Noise Cancellation 5 2.1 Motivation 5 2.1 Circuit Description 7 2.2.1 DPLL 7 2.2.2 DLDO 8 2.2.3 Supply Noise Cancellation Controller 14 2.2.4 DCO 15 2.3 Simulation Results 17 2.4 Experiment Results 19 3. An Injection-Locked Clock Multiplier With Injection Strength Calibration 25 3.1 Motivation 25 3.2 Circuit Description 26 3.2.1 ILCM 26 3.2.2 Charge Pump, Pulse Generator, and Phase Detector 28 3.2.3 Injection Strength Calibrator 30 3.2.4 Voltage-Controlled Oscillator 35 3.3 Analysis 36 3.4 Simulation Results 39 3.5 Experiment Results 43 4. Conclusion and Future Work 49 4.1 Conclusion 49 4.2 Future Work 50 Bibliography 51 | |
| dc.language.iso | en | |
| dc.title | 背景消除供應電壓雜訊的數位鎖相迴路與注入鎖定時脈倍頻器 | zh_TW |
| dc.title | Digital Phase-Locked Loop with Background Supply Noise Cancellation and Injection-Locked Clock Multiplier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 李泰成(Tai-Cheng Lee),林宗賢(Tsung-Hsien Lin),楊清淵(Ching-Yuan Yang),鄭國興(Kuo-Hsing Cheng) | |
| dc.subject.keyword | 數位鎖相迴路,電壓雜訊消除,注入鎖定時脈倍頻器,注入強度校正, | zh_TW |
| dc.subject.keyword | digital phase-locked loop,supply noise cancellation,injection-locked clock multiplier,injection strength calibration, | en |
| dc.relation.page | 53 | |
| dc.identifier.doi | 10.6342/NTU202001647 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-07-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| U0001-2007202013514100.pdf 目前未授權公開取用 | 2.14 MB | Adobe PDF |
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