請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15352
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(CHUNG-PING CHEN) | |
dc.contributor.author | Cheng-Hsien Huang | en |
dc.contributor.author | 黃政憲 | zh_TW |
dc.date.accessioned | 2021-06-07T17:33:10Z | - |
dc.date.copyright | 2020-07-02 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-06-29 | |
dc.identifier.citation | [1] B. Xia, N. Qi, L. Liu and N. Wu, 'A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications,' 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, 2017, pp. 1332-1335. [2] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, 'A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2,' in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009. [3] M. Elsayed, M. Abdul-Latif and E. Sánchez-Sinencio, 'A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS,' 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore, MD, 2011, pp. 1-4. [4] Keliu Shu, E. Sanchez-Sinencio, J. Silva-Martinez and S. H. K. Embabi, 'A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier,' in IEEE Journal of Solid-State Circuits, vol. 38, no. 6, pp. 866-874, June 2003. [5] D. Cai et al., 'A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter,' in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 1, pp. 37-50, Jan. 2013. [6] C. T. Charles and D. J. Allstot, 'A buffered charge pump with zero charge sharing,' 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, 2008, pp. 2633-2636. [7] P. Larsson, 'An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication,' 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), San Francisco, CA, USA, 2001, pp. 74-75. [8] W. S. T. Yan and H. C. Luong, 'A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator,' in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 2, pp. 216-221, Feb. 2001. [9] J. Chuang and H. Krishnaswamy, '19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving −236.2dB jitter-FOM,' 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp. 328-329. [10] K. Sogo, A. Toya and T. Kikkawa, 'A ring-VCO-based sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter,' 2012 Proceedings of the ESSCIRC (ESSCIRC), Bordeaux, 2012, pp. 253-256. [11] Z. Zhang, L. Liu, P. Feng and N. Wu, 'A 2.4–3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, pp. 929-941, March 2017. [12] Y. Lee, T. Seong, S. Yoo and J. Choi, 'A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique,' in IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1192-1202, April 2018. [13] J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. J. Kim and P. K. Hanumolu, 'A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS,' in IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 8-20, Jan. 2017. [14] B. Çatlı et al., 'A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications,' Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, 2013, pp. 1-4. [15] J. K. Panigrahi and D. P. Acharya, 'Performance analysis and design of wideband CMOS voltage controlled ring oscillator,' 2010 5th International Conference on Industrial and Information Systems, Mangalore, 2010, pp. 234-238. [16] X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali and B. Nauta, 'Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector,' in IEEE Journal of Solid-State Circuits, vol. 45, no. 9, pp. 1809-1821, Sept. 2010. [17] P. Agarwal, J. Kim, P. P. Pande and D. Heo, 'Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs,' in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 4, pp. 653-662, April 2018. [18] S. I. Liu, C. Y. Yang, 鎖相迴路. Tsang Hai Book Publishing Co., 2006. [19] J. Zhu, R. K. Nandwana, G. Shu, A. Elkholy, S. Kim and P. K. Hanumolu, '19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS,' 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 338-340. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/15352 | - |
dc.description.abstract | 本論文為一個縫隙雙重取樣之鎖相迴路並採用電容放大技術。在現今5G通訊與穿戴式裝置技術快速的進步下,負責提供參考頻率的鎖相迴路必須朝著小面積、低雜訊的方向努力。然而,鎖相迴路中的低通濾波器往往由被動元件組成,因此佔據了很大的面積。此外,鎖相迴路中的充電汞會因為電流注入和電流分享的效應產生嚴重的參考突波,進而影響鎖相迴路的效能。 本篇論文為了解決上述提及的問題,討論並且提出了解決的辦法。首先,我們使用了電容放大技術,將原本佔據很大面積的低通濾波器,縮小了大約85%的面積。接著,我們使用了一個擁有三個運算放大器的緩衝充電汞,用來減少電流注入與電流分享的效應。最後,為了降低相位雜訊,本篇論文採用縫隙取樣技術,在參考訊號和除頻器輸出的頻率相同且相位差小於180度時,會關閉增益較低的頻率/相位偵測器,改用增益較高的縫隙取樣來鎖相,並且在縫隙取樣時,在每個參考頻率下比較相位兩次,因此在迴路關掉除頻器的同時,將其貢獻的相位雜訊降低至N^2/4,並同時降低參考突波。 本晶片使用台積電90奈米標準CMOS製程,晶片的主動面積為0.0091mm2,供應電壓為1.2V,參考頻率為93.75 MHz,震盪頻率為3 GHz,參考突波為-51dBc,在位移1MHz的相位雜訊為-93 dBc/Hz,方均根的抖動量是1.52ps,峰對峰的抖動量為2.86ps,功率消耗為10.8 mW。 | zh_TW |
dc.description.abstract | This thesis is an aperture double-sampling phase-locked loop with capacitor multiplier technology. With the rapid progress of today’s 5G communication and wearable device technology, phase-locked loop responsible for providing the reference frequency must work towards the small area, and low noise. However, the low-pass filter occupies a large space in phase-locked loop, because it consists of passive components, whose area are large. Moreover, the charge pump in phase-locked loop will generate a serious reference spur due to the effects of charge injection and charge sharing, and affect the performance of the phase-locked loop. To solve the problems mentioned above, this thesis discusses and proposes solutions. First, we used capacitor multiplier technology to reduce the area about 85% of the low-pass filter that originally occupied a large area. Secondly, we used a buffered charge pump with three operational amplifiers to reduce the effects of charge injection and charge sharing. Finally, to reduce phase noise, this thesis uses aperture double-sampling technology. When the frequency of the reference signal and that of the divider output are the same and the phase difference is less than 180 degrees, the frequency / phase detector with lower gain will be turned off. The loop with higher-gain aperture sampling is used to phase lock, and compared the phase twice in each reference period during aperture sampling, so the phase noise contributed by the frequency divider is eliminated, APD/PAC/CP noise becomes N^2/4 times the original while it is turned off, and the reference spur can be scaled down. This chip is fabricated in TSMC 90nm standard CMOS technology. The active area of the chip is 0.0091mm2. The supply voltage is 1.2V. The reference frequency is 93.75 MHz. The oscillation frequency is 3 GHz. The reference spur is -51 dBc. The phase noise at 1MHz shift is -93 dBc / Hz. The rms jitter is 1.52 ps. The peak-to-peak jitter is 2.86 ps. The power consumption is 10.8 mW. | en |
dc.description.provenance | Made available in DSpace on 2021-06-07T17:33:10Z (GMT). No. of bitstreams: 1 U0001-2906202011232500.pdf: 4632150 bytes, checksum: 800f7a757c50aa147a674084ec15bdbc (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | CONTENTS 口試委員審定書 i 誌謝 ii 中文摘要 iii ABSTRACT iv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter 2 Phase-Locked Loop Background 5 2.1 Traditional PLL 5 2.2 Building Blocks of PLL 6 2.2.1 Phase/Frequency Detector and Charge Pump 7 2.2.2 Loop Filter 11 2.2.3 Voltage-Controlled Oscillator 12 2.2.4 Frequency Divider 15 2.3 Linear Model of PLL 16 2.3.1 Linear Model of PFD and CP 16 2.3.2 Linear Model of LPF 17 2.3.3 Linear Model of VCO 18 2.3.4 Linear Model of Frequency Divider 19 2.3.5 Stability Analysis of Phase-locked loop 19 2.4 General Design Procedures of Phase-Locked Loop 24 Chapter 3 A 0.0091 mm2 Aperture Double-Sampling Phase-Locked Loop with Capacitor Technology 25 3.1 Introduction 26 3.2 Architecture 26 3.2.1 Capacitor Multiplier Loop Filter 28 3.2.2 Aperture-Phase Detector and Phase-to-Analog Converter 29 3.2.3 System Analysis 31 3.3 Implement 34 3.3.1 Phase/Frequency Detector with Dead-Zone 34 3.3.2 Buffered Charge Pump 36 3.3.3 Voltage-Controlled Ring Oscillator 38 3.3.4 Differential-to-Single Converter 41 3.3.5 Frequency Divider 42 3.3.6 Clock Generator 44 3.3.7 Aperture-Phase Detector and Phase-to-Analog Converter 45 3.3.8 Switched Charge Pump 49 3.3.9 Capacitor Multiplier Loop Filter 50 3.4 Simulation Result 52 Chapter4 Experimental Results 55 Chpater5 Conclusion and Future work 60 5.1 Conclusion 60 5.2 Future work 61 LIST OF FIGURES Figure 1.1 The charge sharing and the charge injection in the charge pump. 3 Figure 2.1 The conventional PLL. 5 Figure 2.2 Block diagram and transfer curve of an ideal phase detector. 7 Figure 2.3 XOR gate as the phase detector and its timing diagram. 8 Figure 2.4 Block diagram of a traditional phase/frequency detector. 8 Figure 2.5 Timing diagram of the phase/frequency detector. 9 Figure 2.6 Transfer curve of the phase/frequency detector. 9 Figure 2.7 Phase/frequency detector, charge pump and loop filter. 10 Figure 2.8 The timing diagram of PFD, CP and LF. 10 Figure 2.9 The first order loop filter and its transfer curve. 12 Figure 2.10 The second order loop filter and the third order loop filter. 12 Figure 2.11 The voltage-controlled oscillator and its transfer curve. 13 Figure 2.12 The output spectrum of the VCO. 14 Figure 2.13 The relation between spur and ωm. 14 Figure 2.14 The divide-by-4/5 divider. 15 Figure 2.15 Truth table of the divide-by-4/5 divider. 15 Figure 2.16. The first, second and third order low-pass filter. 17 Figure 2.17 A divided-by-4 divider and its timing diagram. 19 Figure 2.18 Linear model of PLL 20 Figure 2.19 The bode plot of the PLL with the maximized phase margin. 22 Figure 3.1 System Architecture. 27 Figure 3.2 Concept of the capacitor multiplier loop filter. 28 Figure 3.3 Concept of APD, PAC and CP. 30 Figure 3.4 Transfer curve of (a) APD, (b) PAC, (c) CP. 30 Figure 3.5 The linear model of the DZPFD_PLL. 31 Figure 3.6 The linear model of the APDPAC_PLL. 31 Figure 3.7 The charge pump current and operation frequency of input and output. 32 Figure 3.9 Schematics phase/frequency detector with dead-zone. 35 Figure 3.10 Phase difference between Vref and Vdiv is large 36 Figure 3.11 Phase difference between Vref and Vdiv is less than 180° 36 Figure 3.12 Schematics of the buffered charge pump. 37 Figure 3.13 Schematics of the operation amplifier. 37 Figure 3.14 (a) The bode plot of OP1, OP2. (b) The bode plot of OP3. 38 Figure 3.15 Schematics of the three-stage voltage-controlled ring oscillator. 38 Figure 3.16 Schematics of the delay cell. 39 Figure 3.17 Half-circuit and small signal analysis of the delay cell. 39 Figure 3.18 The curve of Vcontrol-Frequency of VCO. 41 Figure 3.19 The phase noise of VCO. 41 Figure 3.20 Schematics of the differential-to-single converter. 42 Figure 3.21 Timing diagram of the differential-to-single converter. 42 Figure 3.22 Schematics of the TSPC D-type flip flop. 43 Figure 3.23 Schematics of divide-by-2 divider and divide-by-4 divider. 43 Figure 3.24 Schematics of the clock generator. 44 Figure 3.25 Schematics of the delay cell. 44 Figure 3.26 Timing diagram of the clock generator. 45 Figure 3.27 Schematics of the aperture-phase detector. 46 Figure 3.28 Timing diagram of the aperture-phase detector. 46 Figure 3.29 Schematics of the DFF with reset controlling. 47 Figure 3.30 Schematics of the phase-to-analog converter. 48 Figure 3.31 Timing diagram of PAC. 48 Figure 3.32 Schematics of the switched charge pump. 49 Figure 3.33 The original second-order low-pass filter. 50 Figure 3.34 (a) The bode plot of DZ_PLL (b) The bode plot of APDPAC_PLL 50 Figure 3.35 The capacitor multiplier loop filter. 51 Figure 3.36 Impedance comparison between CMLF original LF 51 Figure 3.37 The environment of measurement simulation. 52 Figure 3.38 The transistor-level simulation result of PLL. 52 Figure 3.39 Spectrum of the pre-layout simulation. 53 Figure 3.40 Spectrum of the final chip. 53 Figure 3.41 Peak-to-peak jitter of the whole chip. 54 Figure 4.1 Layout of the core chip. 55 Figure 4.2 Die photo 55 Figure 4.3 PCB board with the chip. 56 Figure 4.4 Measurement environment. 56 Figure 4.5 Output spectrum of the chip. 57 Figure 4.6 Phase noise of the chip. 58 Figure 4.7 Peak-to-peak jitter of the chip. 58 LIST OF TABLES Table 2.1. The relation between γ and PM 23 Table 3.1 The phase margin and the bandwidth of two loops. 32 Table 4.1 Comparison table. 59 | |
dc.language.iso | zh-TW | |
dc.title | 使用電容放大技術的0.0091mm^2孔徑雙重取樣鎖相迴路
| zh_TW |
dc.title | A 0.0091mm^2 Aperture Double-Sampling Phase-Locked Loop with Capacitor Multiplier Technology | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 盧奕璋(YI-CHANG LU),趙昌博(CHANG-PO CHAO),曹恆偉(HENG-WEI TSAO) | |
dc.subject.keyword | NULL | en |
dc.relation.page | 65 | |
dc.identifier.doi | 10.6342/NTU202001181 | |
dc.rights.note | 未授權 | |
dc.date.accepted | 2020-06-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
U0001-2906202011232500.pdf 目前未授權公開取用 | 4.52 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。