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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林坤佑(Kun-You Lin) | |
| dc.contributor.author | Yu-Chung Hsu | en |
| dc.contributor.author | 許譽鐘 | zh_TW |
| dc.date.accessioned | 2021-05-20T21:27:11Z | - |
| dc.date.available | 2011-08-20 | |
| dc.date.available | 2021-05-20T21:27:11Z | - |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-19 | |
| dc.identifier.citation | [1] IEEE P802.15-05-0596-01-003c.pdf
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Pfeiffer, “A 60 GHz class-E power amplifier in SiGe,” in Asian Solid-State Circuits Conf., Nov. 2006, pp. 199–202. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10408 | - |
| dc.description.abstract | 這篇論文將提出一個可以使用在毫米波頻段的改良式線性器，具有改善互補式金氧半導體功率放大器的功能。在此之前所提出的線性器是使用在40 GHz，並使用了砷化鎵高電子移動率電晶體製程，展現了良好的特性。然而，同樣的架構卻難以在60 GHz頻段有效的移植到互補式金氧半導體製程。因此，我們探討了現性器的詳細運作情形，並提出以相位延遲線來改善普通線性器的改進。另外，我們提出了一個偏壓優化的方法，可以保證針對特定功率放大器可以找到最適合的線性器大小及其控制偏壓。
我們使用90奈米LP互補式金氧半導體來製作一個在60 GHz的功率放大器，並且完全的以提升1 dB衰減點為目標，來做出優化。量測的結果，功率放大器在增益1 dB衰減點呈現了高達14 %的功率附加效率。並且，其還具有15 dB的小訊號增益、13.7 dBm的增益1 dB衰減輸出功率以及15.4 dBm的飽和輸出功率。這是我們所知，在所有發表過的電路中，使用互補式金氧半導體製程在增益1 dB衰減點有最高功率附加效率的60 GHz功率放大器。 | zh_TW |
| dc.description.abstract | In this dissertation, a modified cold-FET pre-distortion linearizer is proposed to improve the linearity of the millimeter-wave CMOS power amplifiers. The previous reported cold-FET linearizer as applied to a 40 GHz power amplifier with a low-loss built-in linearizer in GaAs HEMT technology [6]. However, the effect of the linearizer is not good enough when we try to transplant the technique to 60 GHz using CMOS technology. Therefore, we investigate the operation detail of the linearizer and propose a modified linearizer by adding a delay line. Besides, a bias optimization method that can effectively guarantee the linearity of specific cascode device for power amplifier application is also presented.
A 60GHz cascode power amplifier with modified linearizer is then fabricated under 90-nm LP CMOS technology and fully characterized to enhance its linearity which demonstrated by its extremely well OP1dB. The measurement results of the power amplifier show a power-added-efficiency at OP1dB up to 14% while maintaining 15 dB small signal gain, 13.7 dBm OP1dB and 15.4 dBm Psat. It is the highest power-added-efficiency at OP1dB for millimeter-wave CMOS power amplifiers which ever been published. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T21:27:11Z (GMT). No. of bitstreams: 1 ntu-99-R97942023-1.pdf: 8150624 bytes, checksum: 0ac75654b478088e8652327ea55f288f (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii ABSTRACT iv CONTENTS v LIST OF FIGURES viii LIST OF TABLES xiii Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 2 1.3 Contributions 6 1.4 Dissertation Organization 8 Chapter 2 Linearity of MMW Power Amplifier 9 2.1 Introduction of Power Amplifier 9 2.1.1 Introduction 9 2.1.2 Important Parameters 10 2.2 Linearity Consideration of Power Amplifier 12 2.2.1 Nonlinear Distortion Characterization 12 2.2.2 AM-AM Characteristic 13 2.2.3 Nonlinearity from two-tone input signal 14 Chapter 3 Cold-FET Linearizer with Delay Line 17 3.1 Pre-distortion Linearizer 18 3.1.1 Pre-distortion Technique 19 3.1.2 Loss Characteristic of Pre-Distortion Linearizer 20 3.1.3 Cascading with Power Amplifier 22 3.2 Cold FET Linearizer 25 3.2.1 Introduction 25 3.2.2 Operation Principle 25 3.2.3 Challenge of CMOS Process in V-band 27 3.3 Modified Cold-Mode Linearizer Using Delay Line 29 3.3.1 Guideline to Develop a Modified Linearizer 30 3.3.2 Modified Cold-Mode Linearizer 30 3.3.3 Intuitive Interpretation of the Modification 32 3.4 Operation Detail of Modified Linearizer 33 3.4.1 Analysis of Possible Effects during Operation33 3.4.2 Earlier Saturation Region 36 3.4.3 Lower Current Loss at Saturation Region 41 3.4.4 Varying Resistor Effect 43 3.4.5 Verification of the modified linearizer 49 3.5 Conclusion 52 Chapter 4 A 60GHz Cascode Power Amplifier with Modified Linearizer 53 4.1 Introduction 53 4.1.1 Motivation 53 4.1.2 Objective 54 4.1.3 Design Flow 55 4.2 Previous Published Literatures 57 4.2.1 Cascode Device and the Proposed Power Amplifier 57 4.2.2 Amplifier with Linearizer 58 4.2.3 High PAE Power Amplifier 59 4.3 Pre-Design a Two-Stage Power Amplifier 59 4.3.1 Device Selection 61 4.3.2 One -Stage Power Amplifier 68 4.3.3 Link Budget 71 4.3.4 Conventional Two-Stage Power Amplifier 73 4.3.5 Power Performance at Different Node of Power Amplifier 76 4.4 Integration of Linearizer to Power Amplifier 76 4.4.1 Power Division and Gain compensation 77 4.4.2 Linearizer Size and Control Voltage Selection82 4.4.3 Two-stage Power Amplifier with Modified Linearizer 90 4.5 Measurement Results 97 4.5.1 S-parameter 98 4.5.2 Power Performance 100 4.5.3 IMD3 101 4.5.4 Debug and Discussion 103 4.6 Conclusion 107 Chapter 5 Conclusions 109 REFERENCE 110 | |
| dc.language.iso | en | |
| dc.title | 互補式金氧半導體功率放大器之線性化技術研究 | zh_TW |
| dc.title | Research on Linearization Technique for CMOS Power Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王暉(Huei Wang),蔡政翰(Jeng-Han Tsai),張鴻埜(Hong-Yeh Chang),蔡作敏(Zuo-Min Tsai) | |
| dc.subject.keyword | 功率放大器,60 GHz,高功率附加效率,線性器,V頻段,前置性衰減,線性化技術, | zh_TW |
| dc.subject.keyword | Power Amplifier,PA,High PAE,Linearizer,60 GHz,V-band,Pre-distortion,Linearization Technique, | en |
| dc.relation.page | 114 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2010-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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|---|---|---|---|
| ntu-99-1.pdf | 7.96 MB | Adobe PDF | 檢視/開啟 |
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