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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Hsiao-An Lin | en |
| dc.contributor.author | 林孝恩 | zh_TW |
| dc.date.accessioned | 2021-05-20T21:24:59Z | - |
| dc.date.available | 2012-08-21 | |
| dc.date.available | 2021-05-20T21:24:59Z | - |
| dc.date.copyright | 2010-08-21 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-19 | |
| dc.identifier.citation | [1] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
[2] S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani, “A Network on Chip Architecture and Design Methodology,” Proceedings of Computer Society Annual Symposium on VLSI, pp. 105-112, Apr. 2002. [3] G. De Micheli and L. Benini, Networks on Chips, Morgan Kaufmann, 2006. [4] A. Jantsch and H. Tenhunen (Eds.), Networks on Chip, Kluwer Academic Publishers, 2003. [5] W.J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” Proceedings of Design Automation Conference, pp. 684-689, Jun. 2001. [6] R. Ho, K.W. Mai and M.A. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001. [7] L. S. Peh and W. J. Dally, “A Delay Model and Speculative Architecture for Pipelined Routers,” Proceedings of International Symposium on High-Performance Computer Architecture, pp. 255-266, Jan. 2001. [8] W. J. Dally, “Virtual-Channel Flow Control,” IEEE Transactions on Parallel and Distributed systems, vol. 3, no. 2, pp. 194-205, Mar. 1992. [9] M. Lai, Z. Wang, L. Gao, H. Lu and K. Dai, “A Dynamically-Allocated Virtual Channel Architecture with Congestion Awareness for On-Chip Routers,” Proceedings of Design Automation Conference, pp. 630-633, June 2008. [10] L. S. Peh, “Flow Control and Micro-Architectural Mechanisms for Extending the Performance of Interconnection Networks,” Ph. D. Thesis, Stanford University, Aug. 2001. [11] R. Guerin and V. Peris, “Quality-of-Service in Packet Networks: Basic Mechanisms and Directions,” Computer Networks, vol. 31, no. 3, pp. 169-179, Feb. 1999. [12] E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage and E. Waterlander, “Trade-offs in the Design of a Router with both Guaranteed and Best-effort Services for Networks on Chip,” IEE Proceedings of Computers and Digital Techniques, vol. 150, no.5, pp. 294- 302, Sept. 2003. [13] N. Kavaldjiev, G. J. M. Smit, P. G. Jansen and P. T. Wolkotte, “A Virtual Channel Network-on-Chip for GT and BE Traffic,” Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 211-216, Mar. 2006. [14] C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. S. Yousif and C. R. Das, “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” Proceedings of International Symposium on Microarchitecture, pp. 333-346, Dec. 2006. [15] M. Millberg, E. Nilsson, R. Thid and A. Jantsch, “Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip,” Proceedings of Design Automation and Test in Europe, vol. 2, pp. 890-895, Feb. 2004. [16] Z. Guz, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “Efficient Link Capacity and QoS Design for Network-on-Chip,” Proceedings of Design Automation and Test in Europe, vol. 1, pp. 1- 6, Mar. 2006. [17] M. D. Harmanci, N. P. Escudero, Y. Leblebici and P. Ienne, “Providing QoS to Connection-less Packet-Switched NoC by implementing DiffServ Functionalities,” Proceedings of International Symposium on System-on-Chip, pp. 37-40, Nov. 2004. [18] E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “QNoC: QoS architecture and Design Process for Network on Chip,” Elsevier Journal of Systems Architecture, vol. 50, no. 2-3, pp. 105- 128, Feb. 2004. [19] M. D. Harmanci, N. P. Escudero, Y. Leblebici and P. Ienne, “Quantitative Modeling and Comparison of Communication Schemes to guarantee Quality-of-Service in Networks-on-Chip,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1782- 1785, May 2005. [20] Y.C. Lan, S.H. Lo, Y.C. Lin, Y.H. Hu, and S.J. Chen, “BiNoC: A Bi-directional NoC Architecture with Dynamic Self-Reconfigurable Channel,” Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 266-275, May 2009. [21] S.H. Lo, Y.C. Lan, H.H. Yeh, W.C. Tsai, Y.H. Hu, S.J. Chen, 'QoS Aware BiNoC Architecture' Proceedings of the 24th IEEE International Parallel & Distributed Processing Symposium, pp. 1-10, May 2010. [22] A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha. “Express Virtual Channels: Towards the Ideal Interconnection Fabric,” Proceedings International Symposium on Computer Architecture, pp. 150-161, June 2007. [23] D.C. Gazis, Traffic Science, John Wiley & Sons, 1974. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10380 | - |
| dc.description.abstract | 本文提出一個支援服務質量機制的特性並以預測方式增加效能的雙向通道晶片網路架構，它同時支援了不同服務品質的資料傳輸，使得晶片內部的傳輸效能有所改善。此雙向晶片網路架構允許特定服務品質的資料傳輸時能依其可預期的部份特性以達成傳輸方向預先轉變以及穿透路由器之設計。對於每一個晶片網路的路由器而言，資料通訊的延遲時間以及傳輸吞吐量都受到這個附加的通道靈活性影響而得到更好的效能。這篇論文呈現出一個創新的路由器架構設計以及一個改進控制雙向通道的機制。透過分析可以證明此架構的額外硬體成本是可忽略的。本文利用一個精準時脈週期的測試環境進行模擬，對於在假想的交通型態的傳輸情況下，此雙向通道晶片網路相對於傳統的單向通道架構都能展現出可觀的效能優勢。 | zh_TW |
| dc.description.abstract | A Bidirectional channel Network-on-Chip (BiNoC) architecture with previous direction request and pipeline bypass mechanism is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The Anticipative QoS controlled BiNoC not only allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources but also enhances the latency performance by using penetration and observing previous direction request. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and makes high priority packet be served with better guaranteed performance. In this Thesis, an improved bi-directional on-chip router architecture supporting the hybrid bypass mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulations run on this AQ-BiNoC network under synthetic traffics demonstrate consistent and significant performance advantage over the conventional mesh-grid BiNoC architecture. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T21:24:59Z (GMT). No. of bitstreams: 1 ntu-99-R97943149-1.pdf: 1757713 bytes, checksum: 3dfe50079f0d827cac4d556f7abafd84 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | TABLE OF CONTENTS
ABSTRACT i LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Current Trends in On-chip Communication 2 1.2 Concept of Network-on-Chip 2 1.2.1 Communication Layers in a Network-on-Chip Design 2 1.2.2 Network-on-Chip Architecture 3 1.3 Network Basics 5 1.3.1 Routing 5 1.3.2 Flow Control 6 1.3.3 Performance Evaluation 7 1.3.3.1 Throughput 8 1.3.3.2 Latency 9 1.4 Quality-of-Service 10 1.5 Thesis Organization 11 CHAPTER 2 BACKGROUND KNOWLEDGE 13 2.1 Design of Router Architecture 13 2.1.1 Pipeline of Router Stages 15 2.1.2 Virtual-Channel Flow Control 15 2.2 Quality-of-Service in Network-on-Chip 17 2.3 QoS-aware BiNoC 20 2.3.1 Prioritized VC Management and Inter-router Arbitration 21 2.3.2 Inter-Router Transmission Scheme 22 2.3.3 Bi-directional Channel Routing Direction Control 22 2.4 Express Virtual Channel NoC 24 CHAPTER 3 MOTIVATION 27 3.1 Problem Description 27 3.2 Anticipative Bidirectional Channel Control 30 3.3 Packet Penetration 32 3.4 Pressure Balance 34 3.4 The Proposed Router 34 CHAPTER 4 ROUTER IMPLEMENTATION 35 4.1 Basic Router Design 36 4.2 Anticipative Bidirectional Channel Control 37 4.3 Penetration Ability 38 4.4 Penetration Balance 40 4.5 Proposed Anticipative QoS Controlled BiNoC 41 CHAPTER 5 EXPERIMENTAL RESULTS AND DISCUSSION 43 5.1 Performance Evaluation on Virtual Channel Routers 43 5.2 Synthetic Traffic Analysis 44 5.3 Estimation on Implementation Overhead 72 CHAPTER 6 CONCLUSION 75 REFERENCE 77 | |
| dc.language.iso | en | |
| dc.title | 一個預測性服務質量機制控管的雙向通道晶片網路架構設計 | zh_TW |
| dc.title | Design of an Anticipative QoS Control Bi-directional Network-on-Chip Architecture | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃威(Wei Hwang),熊博安(Pao-Ann Hsiung),楊佳玲(Chia-Lin Yang) | |
| dc.subject.keyword | 晶片網路,路由器,雙向通道,虛擬通道,服務質量, | zh_TW |
| dc.subject.keyword | Network-on-Chip,router,bi-directional channel,virtual channel,Quality-of-Service, | en |
| dc.relation.page | 79 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2010-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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