具耦合齒輪狀閘極與厚薄氧化層結構之金氧半穿隧二極體暫態記憶體

Abstract

本論文旨在探討結合齒輪狀閘極結構（Gear-shaped gate architecture）與非平面厚薄氧化層（High-Low oxide）結構之金氧半穿隧二極體（MISTD）的電性與橫向耦合效應，並深入分析其在暫態記憶體（Transient memory）上的應用潛力。有別於傳統平面結構元件在極端微縮時電流的記憶視窗降低的瓶頸，本研究提出的創新閘極結構，能有效在縮減元件面積的同時，大幅強化暫態電流的記憶視窗。 在第一章中，我們首先回顧了金氧半穿隧二極體的基本電性，以及用於生長氧化層的陽極氧化製程與 Silvaco TCAD模擬軟體的參數設定。第二章探討了平面 MISTD 在暫態記憶體在微縮時的物理限制，並引入創新設計之「耦合齒輪狀閘極結構」。從實驗結果與TCAD模擬皆證實，此結構能藉由高曲率的邊緣強化局部邊緣電場並提升周長面積比，在面積大幅微縮的情況下增強橫向耦合，藉此提升暫態記憶體的效能。而第三章進一步將厚薄氧化層（High-Low oxide）結構整合至元件中，探討其等效微縮之行為。透過在特定區域配置厚氧化層以阻擋非必要的垂直穿隧漏電流，並在邊緣保留薄氧化層以維持關鍵的橫向耦合路徑，此設計成功模擬了元件在微縮下的優異表現。最後，第四章總結本論文之主要研究成果，並針對未來在記憶體技術的發展提出改進建議與展望。

This thesis investigates the electrical characteristics and lateral electrostatic coupling effects of metal-insulator-semiconductor tunnel diodes (MISTDs) featuring a novel coupling gear-shaped gate architecture and a non-planar high-low (HL) oxide structure, comprehensively evaluating their potential for transient memory applications. Addressing the critical bottleneck of memory window degradation in conventional planar devices under aggressive physical scaling, the proposed structural and dielectric innovations effectively minimize the device footprint while substantially amplifying the transient memory window. The thesis is organized as follows. Chapter 1 reviews the fundamental device physics of MISTDs, the anodic oxidation fabrication process, and the parameter configurations for Silvaco TCAD numerical simulations. Chapter 2 explores the physical scaling limitations of planar MISTDs and introduces the coupling gear-shaped gate architecture. Both experimental characterizations and TCAD simulations demonstrate that the high-curvature gear edges intensify localized fringing electric fields and maximize the effective perimeter-to-area ratio. This structural engineering significantly enhances lateral carrier coupling and memory performance despite a drastically reduced device area. Chapter 3 integrates the non-planar HL oxide structure to investigate the "equivalent scaling" behavior of the device. By strategically deploying a thick oxide region to suppress unnecessary vertical tunneling leakage while preserving a thin oxide at the electrode periphery to maintain the critical lateral coupling path, this approach successfully emulates and validates the robust device performance under extreme scaling conditions. Finally, Chapter 4 summarizes the core experimental findings and provides prospects for the future development of capacitor-less memory technologies.