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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10187
標題: | 以0.18-μm CMOS製程製作之30GHz鎖相迴路設計與實現 Design and Implementation of 30 GHz Phase-Locked Loop in a 0.18-μm CMOS Technology |
作者: | Ciao-Ling Peng 彭巧齡 |
指導教授: | 陳中平(Chung-Ping Chen) |
關鍵字: | 鎖相迴路,近橫向電磁傳輸線,毫米波, phase-locked loop,synthetic quasi-TEM transmission line,millimeter-wave, |
出版年 : | 2011 |
學位: | 碩士 |
摘要: | 隨著製程的進步,使得射頻積體電路得以趨向高頻發展。由於無線通訊技術在工業、科學以及醫學等三大領域的快速發展與廣泛應用,市場對低成本、低功耗積體電路的需求有日以劇增的趨勢。為了確保毫米波電路能夠正常地運作,常見的方式即是使用較先進的製程來設計電路,但此一方法卻會導致成本的增加進而降低產品競爭力。因此,成本考量與電路性能之間取得平衡是設計者主要的課題。儘管如此,它仍然是一項具有挑戰性的任務。
在本篇論文中,我們藉由改善電路的架構,使得高頻電路如30.4 GHz鎖相迴路,能夠在0.18-μm標準互補式金氧半導體製程中實現,以達到節省成本的目的。由於電路架構的特性,傳統相位頻率偵測器的操作頻率受到明顯地限制,因此首要之務即是使用獨立的相位偵測器及頻率偵測器。除此之外,在壓控振盪器的設計中,我們引用了近橫向電磁傳輸線的技術來實現小面積及高頻的操作。不僅如此,近橫向電磁傳輸線同時還具備了良好的屏蔽能力,讓壓控振盪器本身更加穩定。除了鎖相迴路的架構介紹外,詳細的量測結果將呈現於本論文之後。藉以驗證上述方法之可行性,此鎖相迴路操作於1.8伏之供應電壓,消耗功率為64.8 mW。 With the advances of the silicon integrated circuit technologies, radio-frequency IC designs are motivated toward higher frequency. Due to the rapid evolution of the wireless communication in industrial, scientific and medical band, the demands for the low-cost and low-power integrated circuit have been increased. To ensure millimeter-wave circuits and systems work properly, the fabrication technology must be scaled down for high-frequency operations. Unfortunately, there exists a tradeoff between cost and circuit performance. However, it is still a challenging task for the designer to implement millimeter-wave circuits while sustaining lower cost efficiently. In this thesis, to reduce the cost of the fabricated circuit, a technique of the circuit topology is adopted such that a 30.4 GHz PLL can be realized in standard CMOS technologies. First, independent PD and FD are employed while the conventional PFD structure limits the operating frequency apparently. In addition, the synthetic quasi-TEM transmission line is introduced to the VCO for the small area and higher operating frequency, facilitating circuit implementation in standard 0.18-μm CMOS technologies. Meanwhile, by using the well-designed transmission line, the VCO can be more stable due to good shielding capability. With a standard design procedure of PLL, the experimental results are presented completely for demonstrations. Operated at a 1.8-V supply voltage, the fabricated circuit consumes a dc power of 64.8mW. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10187 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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ntu-100-1.pdf | 1.44 MB | Adobe PDF | 檢視/開啟 |
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