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  1. NTU Theses and Dissertations Repository
  2. 重點科技研究學院
  3. 元件材料與異質整合學位學程
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101074
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor李敏鴻zh_TW
dc.contributor.advisorMin-Hung Leeen
dc.contributor.author劉恆zh_TW
dc.contributor.authorHeng Liuen
dc.date.accessioned2025-11-27T16:10:05Z-
dc.date.available2025-11-28-
dc.date.copyright2025-11-27-
dc.date.issued2025-
dc.date.submitted2025-10-27-
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101074-
dc.description.abstract螢石結構之氧化鉿鋯展現出於先進電晶體技術中的潛在價值。隨著元件微縮至GAA(Gate-All-Around)與CFET(Complementary FET)架構,對於高介電常數(k)材料在閘極氧化層的需求愈加迫切。藉由其可調控的鐵電性與穩定的高介電特性,HfO₂-基超晶格有望同時達到低漏電、優化臨界電壓控制以及新型非揮發性邏輯功能,成為未來邏輯與記憶體整合的重要材料。
本研究提出兩種基於形態相邊界(MPB)之氧化鉿鋯(HfO₂)超晶格結構,為DZZ,展現出高介電常數(k = 65)、低矯頑場(Ec = 0.8 MV/cm)以及大殘餘極化(2Pr = 41 μC/cm²),並僅需450 °C退火即可符合後段製程(BEOL)需求。 其介電常數的提升來自於離子與電子的共同貢獻,並在正交(Orthorhombic Phase)與四方相(Tetragonal Phase)交替之界面進一步增強。可靠度測試顯示,薄膜於10¹⁰次循環後仍維持 k > 60,2 × 10¹⁰次循環後仍具備2Pr > 30 μC/cm²,且在超過10⁸次1/3 Vop擾動測試下未觀察到明顯衰退。陣列架構與操作機制驗證亦證明DZZ可同時支援DRAM與 NVDRAM (FeRAM)應用,為突破Tera世代記憶體牆提供潛在解決方案。
此外,本研究亦提出應用於電源管理之鐵電閘極堆疊氮化鎵高電子遷移率電晶體(FeMHEMT),可實現雙模操作之E-mode(Vth⁺ = 3.7 V)與D-mode(Vth⁻ = –1.1 V)的動態閾值電壓調控。透過最佳化AMFM:AGaN 比例,有效抑制極化鎖定效應。FeMHEMT在E-mode與D-mode下分別達到VBD = 878 V與900 V,完全符合 12 V供電網路(PDN)之應用需求。耐久性測試亦證實,元件於10⁹次擾動循環後仍可維持穩定的ΔVth = 3 V,展現優異可靠度。E-mode與D-mode FeMHEMT之整合能實現高效率DC-DC轉換器,為異質整合3D PDN系統中電壓調節器提供高效能且具散熱優勢的解決方案。
zh_TW
dc.description.abstractFluorite-phase HfO₂ demonstrates significant potential for advanced transistor technologies. As devices scale to gate-all-around (GAA) and complementary FET (CFET) architectures, the demand for high-k gate dielectrics becomes increasingly critical. By leveraging its tunable ferroelectricity and stable high-k properties, HfO₂-based superlattices can simultaneously achieve low leakage, optimized threshold voltage control, and novel non-volatile logic functionalities, positioning themselves as strong material candidates for future logic–memory co-integration.
In this work, two kinds of morphotropic phase boundary (MPB) based HfO₂ superlattice structures DZZ, are proposed, demonstrating a high dielectric constant (k = 65), low coercive field (Ec = 0.8 MV/cm), and large remnant polarization (2Pr = 41 μC/cm²), with a thermal budget of only 450 °C annealing compatible with Back-End-of-Line (BEOL) processing. The enhancement of dielectric constant originates from the combined contributions of ionic and electronic polarization, further reinforced at domain boundaries formed by alternating orthorhombic and tetragonal phases. Reliability assessments reveal that the films maintain k > 60 after 10¹⁰ cycles, preserve 2Pr > 30 μC/cm² after 2 × 10¹⁰ cycles, and exhibit no observable degradation under 1/3 Vop disturbance stress for more than 10⁸ cycles. Array-level validation further confirms that DZZ can simultaneously support DRAM and NVDRAM (FeRAM) operation, offering a promising pathway to overcome the memory wall in the Tera-generation era.
Furthermore, this work introduces ferroelectric-gated GaN high-electron-mobility transistor (FeMHEMT) for power management applications, enabling dynamic threshold voltage modulation dual-mode operation of E-mode (Vth⁺ = 3.7 V) and D-mode (Vth⁻ = –1.1 V). By optimizing the AMFM:AGaN ratio, the polarization lock effect is effectively mitigated. The FeMHEMT achieves breakdown voltages of VBD = 878 V in E-mode and 900 V in D-mode, fully meeting the requirements of 12 V power delivery network (PDN) operation. Endurance testing further confirms robust reliability, maintaining stable ΔVth = 3 V after 10⁹ disturb cycles. The co-integration of E-mode and D-mode FeMHEMT enables the realization of high-efficiency DC-DC converters, providing thermally advantageous and performance-enhanced voltage regulators for heterogeneous 3D PDN systems.
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dc.description.tableofcontents目次
誌謝 i
中文摘要 ii
Abstract iii
目次 v
圖次 viii
表次 xii
第一章 緒論 1
1.1 先進電晶體技術與發展趨勢 1
1.1.1 背景與動機 1
1.1.2 Backside Power Delivery Network技術解析 3
1.1.3 高介電常數材料之重要性與技術演進 6
1.2 鐵電材料介紹 8
1.2.1 鐵電材料 8
1.2.2 鐵電與反鐵電氧化鉿(HfO2)薄膜系統 10
1.3 極具潛力之新興記憶體材料-反鐵電氧化鉿鋯 12
1.3.1 反鐵電材料的歷史 12
1.3.2 反鐵電材料的特性與物理機制 14
1.3.3 反鐵電高耐力及高速操作特性 15
第二章 文獻回顧 19
2.1 高介電常數二氧化鉿薄膜之發展與沉積溫度工程應用 19
2.1.1 引言:超高密度積體電路對介電材料的需求 19
2.1.2 沉積溫度工程實現Al摻雜HfO2型態相邊界薄膜 19
2.1.3 薄膜製程與退火條件 20
2.1.4 超高介電常數 21
2.1.5 可靠性特徵-耐久性分析 25
2.1.6 效能比較與結論 26
2.2 應用於供電網路(Power Deliver Network, PDN)之先進電晶體整合 28
2.2.1 摘要 28
2.2.2 引言與研究背景 28
2.2.3 CMOS晶片與低電壓氮化鎵(LV-GaN)元件之異質三維(H3D)整合製程 31
2.2.4 LV-GaN之元件特性 32
2.2.5 元件性能基準分析與結論 35
第三章 雙層鐵電電容結構之特性及性能表現 38
3.1 簡介 38
3.1.1 摘要 38
3.1.2 簡介 38
3.2 製程及結構材料分析 41
3.3 基礎特性及性能表現 43
3.3.1 介電特性 43
3.3.2 低矯頑場(Ec)微縮特性與無2Pr損失 46
3.4 結果與討論 50
第四章 利用鐵電閘極堆疊達成增強式(E-mode)與空乏式(D-mode)GaN FeMHEMT 之高效率供電網路應用 52
4.1 簡介 52
4.2 製程及結構材料分析 55
4.3 基礎特性及性能表現 57
4.3.1 極化鎖定效應(Polarization Lock Effect) 57
4.3.2 單一GaN HEMT與MFM的特性 58
4.3.3 雙模操作(Dual-mode)的優化條件 58
4.3.4 E-mode與D-mode的性能表現 60
4.3.5 E-mode與D-mode的穩定性表現 62
4.4 結果與討論 63
第五章 總結與未來展望 65
5.1 總結 65
5.2 未來展望 66
參考資料 67
Publications 76
研討會論文 76
-
dc.language.isozh_TW-
dc.subject形態相邊界-
dc.subject高介電常數-
dc.subject矯頑場-
dc.subject大殘餘極化-
dc.subject後段製程-
dc.subject雙模操作-
dc.subject供電網路-
dc.subjectMorphotropic Phase Boundary (MPB)-
dc.subjectHigh Dielectric Constant (high-k)-
dc.subjectCoercive Field (Ec)-
dc.subjectLarge Remnant Polarization (2Pr)-
dc.subjectBack-End-of-Line (BEOL)-
dc.subjectDual-Mode Operation-
dc.subjectPower Delivery Network (PDN)-
dc.title螢石結構之氧化鉿鋯於先進製程中應用zh_TW
dc.titleFluorite-Structured Hafnium-Zirconium Oxide for Advanced Technology Applicationsen
dc.typeThesis-
dc.date.schoolyear114-1-
dc.description.degree碩士-
dc.contributor.oralexamcommittee蘇彬;陳品光zh_TW
dc.contributor.oralexamcommitteePin Su;Pin-Kuang Chenen
dc.subject.keyword形態相邊界,高介電常數矯頑場大殘餘極化後段製程雙模操作供電網路zh_TW
dc.subject.keywordMorphotropic Phase Boundary (MPB),High Dielectric Constant (high-k)Coercive Field (Ec)Large Remnant Polarization (2Pr)Back-End-of-Line (BEOL)Dual-Mode OperationPower Delivery Network (PDN)en
dc.relation.page77-
dc.identifier.doi10.6342/NTU202504605-
dc.rights.note同意授權(全球公開)-
dc.date.accepted2025-10-28-
dc.contributor.author-college重點科技研究學院-
dc.contributor.author-dept元件材料與異質整合學位學程-
dc.date.embargo-lift2030-10-20-
顯示於系所單位:元件材料與異質整合學位學程

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