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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 黃鐘揚(Chung-Yang (Ric) | |
dc.contributor.author | Kung-Ming Lin | en |
dc.contributor.author | 林拱民 | zh_TW |
dc.date.accessioned | 2021-05-20T21:01:34Z | - |
dc.date.available | 2011-07-27 | |
dc.date.available | 2021-05-20T21:01:34Z | - |
dc.date.copyright | 2011-07-27 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-07-20 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/10095 | - |
dc.description.abstract | 解決布爾可滿足性問題在理論與工業應用上,扮演著極為關鍵角色。十五年來,布爾可滿足性解法器有著長足的進展,得以解決相當大型的問題。為了進一步解決更大型、更困難的布爾可滿足性問題,平行化布爾可滿足性解法器於近年來受到相當關注。最近幾年的國際布爾可滿足性解法器比賽之中,最佳的四至八線程平行化布爾可滿足性解法器的成績勝過最佳單線程布爾可滿足性解法器。
通用計算於圖形處理單元也在大量平行運算的領域之中興起。為了探討大量平行化布爾可滿足性解法器的概念,我們運用計算統一設備架構的平台,實現了名為「CUDASAT」的子句分享平行化、衝突驅使子句學習、戴維斯-普特南-羅格曼-羅夫蘭演算法布爾可滿足性解法器。 根據我們瞭解,目前尚未有類似CUDASAT的程式。實驗結果顯示,提昇平行解法器的數量時,平均每個解法器於搜尋上所用的步驟有著明顯下降的趨勢。CUDASAT的效能無法與現今最好的平行化布爾可滿足性解法器相比。它是作為發展大量平行化、低成本、替代性布爾可滿足性解法器的原型。 | zh_TW |
dc.description.abstract | Boolean satisfiability (SAT) problem plays a critical role in theoretical and industrial applications. With the advance of SAT solvers in the past 15 years, we are capable to solve fairly large-scale problems. To improve the performance of SAT solvers for much larger and harder SAT problems, parallelization of SAT solvers is gaining much attention in recent years. The state-of-the-art 4-to-8 threaded parallel SAT solvers are more powerful than single-threaded ones in recent international SAT solver competitions.
General-Purpose computation on Graphics Processing Units (GPGPU) is also emerging from massive parallel computing realm. To explore the concept of massive parallel SAT solvers, we have implemented the “CUDASAT”, a parallel CDCL-DPLL (Conflict Driven Clause Learning - Davis-Putnam-Logemann-Loveland) SAT solver with clause sharing on CUDA (Compute Unified Device Architecture) platform. To the best of our knowledge, CUDASAT is the first of its kind. The experimental results demonstrated a downward trend in average searching events per solver while increasing the number of parallel solver. While the performance is not comparable to those state-of-the-art parallel SAT solvers, CUDASAT serves as a prototype of massive parallelization toward an affordable and alternative solution for SAT solving. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T21:01:34Z (GMT). No. of bitstreams: 1 ntu-100-R98943080-1.pdf: 4966609 bytes, checksum: f3153a5f4a8f8ea22298f75ec085d6df (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii Abstract iii Contents iv List of Figures vii List of Tables xi Chapter 1 Introduction 1 Chapter 2 Previous Work 4 2.1 The Categories of SAT Solvers 4 2.2 Parallel SAT solvers 5 2.2.1 Plingeling and ManySAT 7 2.2.2 Decision Divergence and Learnt Clauses Exchange 8 2.3 SAT Solvers on CUDA 8 Chapter 3 Preliminaries 10 3.1 Boolean Satisfiability 10 3.1.1 Definitions 10 3.1.2 SAT Applications 14 3.2 Compute Unified Device Architecture (CUDA) 15 3.2.1 Hardware Architecture 15 3.2.2 Programming Model 16 Chapter 4 CUDASAT 24 4.1 Overview of CUDASAT 24 4.1.1 Massive Parallelization 24 4.1.2 GPGPU vs. CPU 24 4.1.3 CUDASAT: A Parallel SAT Solver on CUDA 26 4.2 Program Overview 28 4.3 Solver Phase 32 4.3.1 DPLL (Davis-Putnam-Logemann-Loveland) Algorithm 33 4.3.2 Boolean Constraint Propagation (BCP) 35 4.3.3 Two-Watched-Literal Scheme 37 4.3.4 Conflict Analysis 39 4.3.5 Clause Learning 41 4.3.6 The First Unique Implication Point (UIP) 42 4.3.7 Non-Chronological Back-Tracking 43 4.4 Shared Learnt Clauses 45 4.5 Memory Management 48 Chapter 5 Experimental Results 50 5.1 Description of Cases 50 5.2 Environment Setup 51 5.3 Experimental Results 52 5.3.1 Industrial SAT Problem: logistics.b 52 5.3.2 Comparison of Configurations: logistics.b 61 5.3.3 Discussion: logistics.b 62 5.3.4 Industrial UNSAT Problem: qg4-08 64 5.3.5 Comparison of Configurations: qg4-08 73 5.3.6 Discussion: qg4-08 74 5.3.7 Random SAT Problem: f150s 76 5.3.8 Comparison of Configurations: f150s 85 5.3.9 Discussion: f150s 86 5.3.10 Random UNSAT Problem: f100u 87 5.3.11 Comparison of Configurations: f100u 96 5.3.12 Discussion: f100u 97 Chapter 6 Conclusions and Future Work 98 Reference 99 | |
dc.language.iso | en | |
dc.title | 運用計算統一設備架構實現之平行化布爾可滿足性解法器 | zh_TW |
dc.title | Implementation of Parallel Boolean Satisfiability Solver by CUDA (Compute Unified Device Architecture) | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 江介宏(Jie-Hong (Roland),鄭振牟(Chen-Mou (Doug) | |
dc.subject.keyword | 布爾可滿足性問題,可滿足性解法器,平行運算,衝突驅使子句學習,戴維斯-普特南-羅格曼-羅夫蘭,通用計算於圖形處理單元,計算統一設備架構, | zh_TW |
dc.subject.keyword | Boolean satisfiability problem,satisfiability solver,parallel computing,SAT,CDCL,DPLL,GPGPU,CUDA, | en |
dc.relation.page | 116 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2011-07-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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