http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91865 Mon, 05 Oct 2026 10:55:58 GMT 2026-10-05T10:55:58Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93460 標題: 離子敏感型場效電晶體設計於Troponin I感測之研究; An Implementation of Ion Sensitive Field Effect Transistors for Troponin I Detection 作者: 滑凱茵; Hoi-Yan Wat 摘要: 隨著全球各國陸續進入高齡化的社會，醫療問題顯得日益重要，根據多項研究指出，心血管疾病佔據所有疾病死因之冠，如急性心肌梗塞等都是人類健康的一大威脅。 因此，本篇論文主要探討如何製作出一個有良好穩定度，精確又能快速檢驗的生物感測器。我們將從半導體元件設計為核心，採用不同結構、不同面積、並進一步針對感測膜材料進行談討。再者，我們使用表面改質的方法，使表面種上抗體，使元件能有效檢測出抗原的濃度。接著，進行選擇比測試，說明元件具有的專一性吸附的特性。最後進行穩定度測試，驗證何種感測膜能夠有最少的時間飄移，以減少元件所造成的誤差。 在這篇論文中，我們驗證了多種大小、不同材料的元件，得到Al2O3有良好的穩定性，同時最大面積的Al2O3感測膜靈敏度甚至能夠達到50.4 mV/decade 的Troponin I量測。若未來能進一步結合大數據的資料及AI模型的訓練，將能夠有效解決時間飄移的問題，使臨床上有更穩定的表現，實現快速，精準的醫療檢測器。; As global populations continue to age, healthcare issues become increasingly important. Numerous studies have identified cardiovascular diseases as the leading cause of mortality, presenting significant threats to human health, including acute myocardial infarction. This paper addresses the development of a stable, precise, and rapid biosensor. It focuses on semiconductor device design, exploring various structures and areas, and deep into discussions regarding sensing membrane materials. Additionally, surface modification techniques are employed to immobilize antibodies on the surface, enabling effective detection of antigen concentrations. Subsequent selectivity tests demonstrate the specificity of the device. Finally, stability tests are conducted to discover which sensing membrane exhibits minimal drift over time. Through this study, we validate multiple devices of varying sizes and materials, identifying Al2O3 exhibited excellent sensitivity and stability. Furthermore, the largest area Al2O3 sensing membrane demonstrates a sensitivity of up to 50.4 mV/decade for Troponin I measurement. We hope to have the integration of big data and AI model training in future research holds promise for effectively addressing drift issues, leading to more stable performance in clinical settings and facilitating rapid and accurate medical diagnostics. Mon, 01 Jan 2024 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93460 2024-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101838 標題: 鍺 PIN 光偵測器之溫度相依光學與電性分析; Temperature-Dependent Optical and Electrical Analysis of Germanium PIN Photodetectors 作者: 俊杰; LOGESHWARAN VENKATESAPANDIAN 摘要: 由於鍺（Germanium）具備與 CMOS 製程兼容的特性，且在通訊波段具有強大的吸收能力，因此鍺 PIN 光電偵測器被廣泛應用於矽光子平台的近紅外光學互連。然而，在高效能運算系統（HPC）與高密度光子積體電路（PIC）等實際環境中，光電偵測器經常在變動的溫度條件下運作。由於鍺的材料特性與載子傳輸機制具有高度的溫度依賴性，因此深入了解由溫度引起的性能權衡（Trade-offs），對於設計可靠的高速光電偵測器至關重要。 本論文針對傳統側向 PIN 型鍺光電偵測器（Lateral Ge PIN Photodetector）在 1310 nm 波段下的光學與電學行為，進行了系統性的物理基礎研究。研究中採用了光電耦合模擬框架：首先利用 ANSYS Lumerical FDTD 獲取光吸收與載子產生分布圖（Carrier generation profiles），隨後將其匯入 ANSYS Lumerical CHARGE 進行電學傳輸分析。透過此工作流程，本研究在寬溫度範圍內評估了多項關鍵性能指標，包括：暗電流、響應度、量子效率、瞬態響應、電容以及 3-dB 頻寬。 我們設計了一款長度為 15 μm 的鍺PIN 光電偵測器。研究結果顯示，暗電流隨著溫度的升高而顯著增加，這主要是由於能隙減小（Bandgap narrowing）以及更強的熱激發（Thermal excitation） 導致本身的載子濃度提升所致。相較之下，偵測器在高溫下表現出更佳的光吸收能力。在 −1 V 偏壓下，其響應度從 250 K 時的 0.265 A/W 增加到 350 K 時的 0.30 A/W 。這種性能是由於於溫度引起的鍺消光係數（Extinction coefficient） 與吸收係數（Absorption coefficient） 的增加，進而導致更強的光子吸收與載子產生率。 然而，元件的性能會隨溫度升高而退化。在 −1 V 偏壓下，所得到的 3-dB 頻寬從 250 K 時的 50 GHz 單調下降至 350 K 時的 44.4 GHz，這展現了明顯的響應度與頻寬之間的權衡關係（Responsivity–bandwidth trade-off）。這種頻寬減小主要是由溫度依賴的載子傳輸退化所主導：隨著溫度升高，聲子散射（Phonon scattering） 變得劇烈，進而降低了載子的遷移率（Mobility）與飽和速度（Saturation velocity）。這導致載子穿越時間（Transit time）增加，最終降低了受限於穿越時間的頻寬。 瞬態光電流（Transient photocurrent） 模擬進一步證實了此現象：在較高溫度下，光電流的幅值（Magnitude） 較高，但響應動態（Response dynamics） 卻因此變慢。最後，透過將總頻寬分解為 RC 受限頻寬（RC-limited） 與穿越時間受限頻寬（Transit-time-limited） 兩個分量，我們利用解析計算（Analytical calculations）驗證了模擬出的頻寬趨勢，結果顯示計算值與模擬值高度吻合。總體而言，本論文建立了關於溫度如何影響鍺 PIN 光電偵測器性能的清晰認知，並強調了在設計可靠的高速矽光子接收器時，進行溫度感知建模（Temperature-aware modeling）與優化的重要性。; Germanium PIN photodetectors are widely used in silicon photonics platforms for near-infrared optical interconnect applications due to their CMOS compatibility and strong absorption at telecommunication wavelengths. However, in practical environments such as high-performance computing systems and dense photonic integrated circuits, photodetectors often operate under varying thermal conditions. Since germanium material properties and carrier transport mechanisms are highly temperature dependent, understanding the temperature-induced performance trade-offs is essential for reliable high-speed photodetector design. This thesis presents a systematic physics-based investigation of the temperature-dependent optical and electrical behavior of a conventional lateral Ge PIN photodetector at 1310 nm. A coupled optical–electrical simulation framework was employed, in which the optical absorption and carrier generation profiles were first obtained using ANSYS Lumerical FDTD, and then imported into ANSYS Lumerical CHARGE for electrical transport analysis. Using this workflow, key performance metrics—including dark current, responsivity, quantum efficiency, transient response, capacitance, and 3-dB bandwidth—were evaluated over a wide temperature range. We demonstrate a 15 μm-long Ge PIN photodetector where the results show that dark current increases significantly with temperature, mainly due to enhanced intrinsic carrier concentration caused by bandgap narrowing and stronger thermal excitation. In contrast, the detector exhibits an improved optical absorption at elevated temperature as the responsivity increases from 0.265 A/W at 250 K to 0.30 A/W at 350 K under −1 V bias. This enhancement is attributed to temperature-induced increases in the extinction coefficient and absorption coefficient of Ge, leading to stronger photon absorption and improved carrier generation. However, the high-speed performance degrades with temperature. The extracted 3-dB bandwidth decreases monotonically from 50 GHz at 250 K to 44.4 GHz at 350 K at −1 V, demonstrating a clear responsivity–bandwidth trade-off. This bandwidth reduction is dominated by temperature-dependent carrier transport degradation, where phonon scattering reduces mobility and saturation velocity, increasing carrier transit time and reducing the transit-time-limited bandwidth. Transient photocurrent simulations further confirm this behavior, showing higher photocurrent magnitude at elevated temperature but slower response dynamics. Finally, the simulated bandwidth trends were validated through analytical calculations by decomposing the overall bandwidth into RC-limited and transit-time-limited components, showing close agreement between calculated and simulated values. Overall, this thesis establishes a clear understanding of how temperature affects the performance of Ge PIN photodetectors, highlighting the importance of temperature-aware modeling and optimization for reliable high-speed silicon photonic receiver design. Thu, 01 Jan 2026 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/101838 2026-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104370 標題: 邁向記憶體內運算之氧化物半導體電晶體電性調變技術; Electrical Modulation of Oxide Semiconductor Field-Effect Transistors for In-Memory Computing Applications 作者: 李姵穎; Pei-Ying Li 摘要: 隨著人工智慧運算需求持續增加，記憶體內運算（Computing-in-Memory, CIM）已成為突破傳統 Von Neumann 架構所造成之資料搬移瓶頸的重要技術。其中，以氧化物半導體電晶體（Oxide Semiconductor Field-Effect Transistor, OSFET）實現之 2T0C DRAM 因具備非破壞性讀取及良好的資料保持特性，而被視為具潛力之記憶體與類神經突觸元件。然而，OSFET 普遍存在臨界電壓（threshold voltage, VT）偏負的問題，因此如何有效調控其臨界電壓，已成為提升元件實用性的關鍵課題。 本論文採用閘極堆疊工程進行 OSFET 之臨界電壓調變，透過設計三種不同閘極堆疊結構（Baseline、WIZ 與 WISZ），成功實現約 ±30 mV 之雙向臨界電壓調變，同時維持相近之導通電流（on-current, ION）與次臨界擺幅，有望突破傳統臨界電壓調變方法中 VT–ION trade-off 的限制。接著，為進一步驗證其於記憶體及神經形態運算之應用潛力，本研究將上述 OSFET 元件應用於 2T0C DRAM 與類神經突觸元件。實驗結果顯示，採用較高臨界電壓之 OSFET 可有效降低關閉漏電流，進而減緩儲存節點電荷的流失，並提升 2T0C DRAM 之資料保持能力。此外，透過降低 2T0C 架構中讀取電晶體的閘極漏電流，可維持較高的儲存節點電壓，進而改善突觸元件之電導調變線性度與電導開關比，並提升神經網路之分類準確率。綜合上述結果，本研究不僅展示了 OSFET 之臨界電壓調變技術，更進一步提升了 OSFET 2T0C DRAM 之資料保持能力及神經網路準確率，顯示其於記憶體內運算及人工智慧硬體具有良好的應用潛力。; With the increasing demand for artificial intelligence (AI) computing, Computing-in-Memory (CIM) has emerged as a promising solution to overcome the data movement bottleneck of the conventional Von Neumann architecture. Among various memory technologies, oxide semiconductor field-effect transistor (OSFET)-based 2T0C DRAM has attracted considerable attention owing to its non-destructive read operation, excellent data retention, and potential for neuromorphic applications. However, the inherently negative threshold voltage (VT) of OSFETs limits their practical applications. In this work, gate stack engineering is employed to modulate the threshold voltage of OSFETs. Three gate stack structures, namely Baseline, WIZ, and WISZ, achieve bidirectional VT modulation of approximately ±30 mV while maintaining comparable on-current (ION) and subthreshold swing, showing the potential to overcome the conventional VT–ION trade-off. Furthermore, the proposed OSFETs are applied to 2T0C DRAM and synaptic devices. The results demonstrate that a higher-VT OSFET effectively suppresses leakage current and improves the data retention of the 2T0C DRAM. Moreover, reducing the gate leakage current of the read transistor improves synaptic performance, leading to higher neural network classification accuracy. Overall, this work demonstrates an effective VT engineering approach for OSFETs and the potential of OSFET-based 2T0C DRAM for CIM and AI hardware applications. Thu, 01 Jan 2026 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/104370 2026-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98933 標題: 透過背閘極高介電常數基板預處理優化二硒化鎢P型場效電晶體; Optimization of WSe2 P-Type FET through Back Gate High-k Substrate Pretreatment 作者: 邱英展; Ying-Zhan Chiu 摘要: 本研究針對單層二硒化鎢所構成之增強型電洞載子全局背閘極場效電晶體以及雙閘極場效電晶體進行製程開發與電性優化，並探討高介電常數閘極氧化層的品質與雙閘極結構對元件開關性能的影響。 本作的背閘極基板為氮化鈦做為閘極基底，其上方是以原子層沉積製備之八奈米厚的二氧化鉿作為背閘極氧化層，本作將透過氮氫混和氣體退火與氧電漿進行氧化層預處理，用以提升背閘極氧化層及其作為高介電常數氧化層與二維材料介面的品質。緊接著使用濕式轉移法將單層二硒化鎢轉移至經過預處理的目標基板上，並以光微影技術定義源極/汲極之電極與上電極圖案，完成具全局背閘極與上閘極的雙閘極電晶體結構。 經實驗結果顯示，經氧化層預處理之二氧化鉿基板能有效降低界面態密度，使得元件的次臨界擺幅、臨界電壓、遲滯與導通電流皆有明顯改善。在進一步導入上閘極後，在不犧牲其他電性表現的前提下，得益於雙閘極良好的協作以及更優異的閘極控制能力，使得元件能夠在臨界電壓往更理想的方向推動，並且在次臨界區的擺幅能夠進一步下降，展現出良好的雙閘極調控效果。 本研究結果證明，藉由介面預處理優化與閘極堆疊的工程，能夠有效提升單層二硒化鎢電晶體整體的電性表現，為二維材料於低功耗邏輯元件之應用提供新的方向與參考。; This study develops fabrication processes for p-type enhancement-mode global back-gate FETs and dual-gate FETs based on monolayer WSe₂, and evaluates how high-k gate-oxide quality and dual-gate architecture influence switching performance. Devices use TiN as the back-gate electrode with an 8 nm HfO₂ dielectric deposited by ALD, followed by forming-gas annealing and O₂-plasma pre-treatments to improve oxide quality and the WSe₂/oxide interface. A monolayer WSe₂ is wet-transferred onto the treated substrate, and optical lithography defines the source/drain contacts and a local top gate, forming a dual-gate structure. Pre-treated HfO₂ markedly lowers interface-trap density, yielding better subthreshold swing, threshold voltage, hysteresis, and on-current. Adding the top gate further strengthens electrostatic control without sacrificing other metrics: the threshold voltage moves closer to the ideal case and the subthreshold swing further improves, demonstrating effective dual-gate modulation. These results show that interface pre-treatment combined with gate-stack engineering can significantly enhance monolayer WSe₂ transistor performance, providing guidelines and benchmarks for low-power logic applications based on 2-D materials. Wed, 01 Jan 2025 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98933 2025-01-01T00:00:00Z