http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/161 Fri, 10 Apr 2026 19:48:21 GMT 2026-04-10T19:48:21Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52321 標題: 高頻譜純度無線發射機之射頻電路技術; RF Circuit Techniques for Wireless Transmitter with High Spectral Purity 作者: Kun-Yao Kao; 高堃堯 摘要: 近二十年，我們見證了無線通訊的巨大成長。對於低成本、節能、微小化、可支援多種數位通信標準之通訊設備日益增長的需求，促進了射頻收發機積體電路獲得越來越多的發展。在設計發射機路徑時，必須要保持發射信號的高頻譜純度，以避免電路內非線性現象引起的頻帶外發射以及信號雜訊比的降低。 本篇論文描述了發射機路徑上的兩個關鍵基本組件，亦即壓控振盪器和功率放大器。首先本文起於發射機路徑上頻譜純度的重要性，由一給定的發射頻譜波罩探討發射機所需壓控振盪器和功率放大器的非線性規格。本文所提出的第一個電路是一個採用互補式變壓器耦合的壓控振盪器，其具有抑制來自切換對之通道熱雜訊的功能。相較於其它現有架構，可本質上改善相位雜訊以及振盪器之雜訊因子。為了深入分析相位雜訊的非線性機制，我們將回顧過去定量分析相位雜訊的理論。本文所提出的第二個電路是兩個結合相位延遲線性器之功率放大器，其可更加展延輸出功率1 dB壓縮點。電路中的非線性所引起的三階諧波失真和鄰近波道功率比將分為振幅失真以及相位失真來討論，透過加入一斜率補償的線性器，可使在複雜的數位調變下之功率倒退操作更加有效率。; The last two decades have witnessed a tremendous growth in wireless communications. The increasing demands for cost-effective, power-efficient, and miniature size communication devices that support multiple digital communication standards have lead more and more developments on the integration of radio-frequency (RF) transceiver circuitry. For the transmitter path design, keeping transmitted signal with high spectral purity is essential to prevent the out-of-band emission and the reduction of signal-to-noise ratio (SNR) generated from the circuit nonlinearities. This thesis describes the circuit design for the two crucial building blocks in the transmitter path, namely voltage-controlled oscillator (VCO) and power amplifier (PA). The significance of spectral purity in the transmitter path is arisen at the beginning. From a given spectrum emission mask to the required nonlinear specification for the VCO and PA is discussed. The first circuit design is a complementary transformer-coupled VCO proposed to suppress the channel thermal noise coming from the switching pair, which substantially results in lower phase noise performance and a lower oscillation noise factor compared with the existing VCO architectures. In order to analyze the nonlinear phase noise mechanism in depth, the quantitative theoretical framework will be reviewed. The second circuit design is two power amplifiers (PAs) with individual phase-delay pre-distortion linearizer proposed to further extend the output 1 dB compression point (OP1dB). The impact due to circuit nonlinearity on the third-order intermodulation distortion (IMD3) and the adjacent channel power ratio (ACPR) is discussed with separate amplitude/phase distortion issues. By means of adding a slope compensation linearizer, the power back-off operation is more efficient under complex digital modulation scheme. Thu, 01 Jan 2015 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52321 2015-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55448 標題: 高頻/高速差動電路電磁輻射之研究與解決方案; Designs and Solutions of the Electromagnetic Radiation from High Frequency/High-speed Differential Circuit Systems 作者: Hung-Chuan Chen; 陳泓銓 摘要: 本論文著重於差動信號在射頻系統與高速數位系統內造成的電磁輻射影響並提出電磁輻射改善策略。在差動信號介面下，由不理想效應造成的共模雜訊被視為是產生嚴重輻射問題的主因。因此，共模雜訊於差動射頻系統內的影響為首要探討的機制。經研究發現，當射頻系統內的天線受共模雜訊干擾時，會導致天線同極化場型的最大增益方向改變且交叉極化場型會大量增加，使得天線的輻射場型與原設計不同。為解決此問題，提出適用於差動射頻系統且具有高共模雜訊抑制功能的平衡式帶通濾波器。為求微小化，不以傳統半波長共振結構的方式設計，另提出兩種新穎的四埠集總元件架構，分別為電感式耦合與電容式耦合，達成平衡式帶通濾波器的設計，該濾波器於差模信號傳送時可提供帶通響應，而於共模雜訊操作下可達到抑制的效果，且其共模電路架構引入可任意調整的傳輸零點，使具有抑制平衡式天線的共模共振機制，而其所設計出的平衡式帶通濾波器面積僅有0.114 λg × 0.1 λg，並且可於差模傳送頻帶內量測到至少50 dB且最大值約有67 dB的超高共模雜訊抑制比，相較其它已發表的電路架構，是共模抑制能力最好的設計。只要將其平衡式帶通濾波器擺放在射頻系統的天線端前，即可確保天線的輻射場型不受共模雜訊干擾。 針對高速差動數位系統，主要研究來自於電路板模組的電磁輻射問題，經研究發現其中與各電路板相連的連接器，是產生高頻輻射的主要來源。傳統上，為解決連接器內因轉角造成的長度不等長而造成的共模雜訊，導致信號完整度的議題，長度補償技巧是常用的解決方案。經本研究指出，該技巧的確能改善信號的傳輸品質，且差模信號轉成共模雜訊的成分約略有10 dB降低，但卻無法改善連接器本身造成的電磁輻射問題。根據連接器的電流分布發現，連接器造成的電磁輻射與結構產生的天線模態電流有關，而非與結構不對稱造成的共模電流相關。進一步研究連接器本身的輻射特性，則發現造成電磁輻射峰值的頻率，是來自於連接器的側接地線與背接地線形成類似槽孔天線的輻射機制，依據天線模態電流分布，連結器於該頻段內產生半波長及其諧波的共振，產生大量的輻射。此外，當兩兩相鄰的側接地線或背接地線產生寬邊耦合效應時，會進一步產生新的共振機制，產生更多的電磁輻射峰值，惡化了連接器的電磁輻射響應。 為降低連接器於高頻的電磁輻射特性，本研究提出三種作法。首先，針對位處於連接器的最內側與最外側的非對稱差動信號對，提出額外引進側接地線，使其差動信號對變得對稱，改善差動信號對的模態轉換並且提供降低電磁輻射的功能。另一種降低輻射量的方法是在連接器的四周圍貼上損耗材質的貼片，該方式經實驗驗證可達到大約6 dB的輻射衰減量，且該作法並不會惡化連接器的信號傳輸品質。最後一種方式是針對產生輻射的槽孔結構進行改善，直接將側地線與背接地線以金屬導體相連，除去連接器內的槽孔結構，該作法可大幅降低輻射達到約25dB的抑制，並且亦可改善連接器的信號傳輸品質，達到信號完整度與電磁干擾的共設計。; This dissertation is concentrated on studying the radiated emissions from differential RF system and high-speed differential digital system and therefore presenting radiation mitigation strategies. At the differential signaling interface, common-mode noise has been considered as the source of producing server radiation issues. Thus, the influence of the common-mode noise on differential RF system is studied. As the antenna is coupled with common-mode noise, the peak gain of co-polarization is rotated and the cross-polarization level is significantly increased. In order to solve this problem, balanced bandpass filters with high common-mode rejection level are proposed and applied to the RF differential system. Without designing the filter using half-wavelength resonator, new four-port lumped-element circuit topologies with inductive coupling method and capacitive coupling method are presented. The newly circuit topologies can support bandpass response under differential-mode operation and exhibit bandstop filtering function under common-mode noise. Moreover, the proposed circuit topologies can have additional transmission zero to prevent the common-mode resonant mechanism of the balanced antenna. The implemented balanced bandpass filter occupies a compact size of 0.114 λg × 0.1 λg with superior CMRR of 50 dB within the differential-mode passband and approximately 67 dB in maximum, which show the best performance compared to the other works. As inserting the proposed balanced bandpass filter before the antenna, it can prevent the antenna’s operation from the common-mode noise. For high-speed differential digital system, radiated emissions over GHz are mainly attributed to the connector across multiple circuit boards. Due to the bends along the connector, skew compensation strategies are commonly used to correct the imbalance length for reducing common-mode noise as well as improving signal quality. Although over 10 dB reduction on the mode conversion of |Scd12| can be observed, the total radiated power from connector is not significantly reduced. According to the current distributions, it shows that the radiated emission is strongly related to the antenna-mode currents, instead of common-mode currents. It is further discovered that the radiation peak is caused by the slot-like antenna, which is formed by the edge ground blade and back ground blade. Based on the antenna-mode current distributions, the radiation peaks are the integer multiples of a half-wavelength. In addition, as multiple wafers are considered within the connector, additional radiation peaks are produced due to the slots between wafers. It makes the radiation performance of the connector even worse. Three radiation mitigation methods are proposed. One is to insert additional edge ground blade to the orphaned differential pairs, which are located at the wafer periphery. This strategy can make the radiated emission level lower and improve mode conversion, because the orphaned differential pairs with inserted edge ground blade become symmetrical. Another is to attach lossy material to cover the entire connector. Over 6 dB suppression on the radiated emission can be obtained. Furthermore, the attached lossy material does not degrade the signal quality through the connector. The other is to remove the slot structures inside the connector by connecting the ground blades together. Approximately 25 dB suppression on the total radiated power is given and the signal quality of the connector is also improved. This technique can benefit both SI and EMI issues for the high-speed connector. Wed, 01 Jan 2014 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/55448 2014-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45392 標題: 高速電子遷移率電晶體及互補式金氧半場效電晶體之微波功率放大器之研究; Research of HEMT and CMOS Microwave Power Amplifier 作者: Ping-Sung Chi; 紀秉松 摘要: The goal of this thesis is to design and implement four power amplifiers, two in pHEMT and two in CMOS processes, including two X-band high efficiency power amplifiers, a 24 GHz balanced amplifier, and a K-band power amplifier. The first part of the thesis presents a harmonic tuned power amplifier at X-band. Adding harmonic loading circuits at the output and the input of the transistor can improve the overall output power and power added efficiency of the power amplifier. The circuit is designed in 0.15-μm low-noise pHEMT technology and has a measured maximum PAE of 48.5% at 10.5 GHz. An abrupt flush of the drain current is obtained in measuring this amplifier, and the measurement phenomenon and mechanism of the abrupt flush of the drain current due to reverse gate current are also investigated in this part. The second part focuses on the design of high power amplifier at 24 GHz using 0.15-μm power pHEMT technology. Two 8 finger 800-μm devices are combined in a current method in the two-stage PA, and then using the balanced configuration combines two same two-stage PAs again. Considering the process variation of small capacitors in the circuit design, re-simulation results show good agreement with measurements. The re-design results indicate that the odd mode oscillation is illuminated and process variation only has less effect on the circuit. The third part shows an X-band power amplifier with the high PAE and the small chip size using 0.18-μm CMOS process. In order to obtain wide bandwidth at power and PAE performance, broadband output and input matching network are adopted in this power amplifier. From the measurements, the power amplifier obtained the best PAE of 25.7% and saturation output power of 23.8dBm at 9.5 GHz. Besides, this PA demonstrates the 1-dB power bandwidth from 7.8 to 11 GHz and the PAE insides this bandwidth all exceed 20%. To our knowledge, this is a power amplifier with the highest PAE, the smallest chip size to date in CMOS process at X-band. The final part presents a K-bnad high power amplifier with the wide power bandwidth implemented by 0.13-μm CMOS technology. Broadband output power matching and broadband input conjugate matching lead to good power and PAE performances at the designed band. This PA achieves a measurement saturation output power of 18.6 dBm at 24 GHz with a power bandwidth of 6.5 GHz, and the PAE all exceeds 10% at this bandwidth. To our knowledge, this is a power amplifier with the widest power bandwidth and high saturation output power to date in CMOS process at K-band. Index Terms—power amplifier (PA), X-band, K-band, pHEMT, CMOS, monolithic microwave integrated circuit (MMIC), high efficiency, high power, reverse gate current, wide power bandwidth. Thu, 01 Jan 2009 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/45392 2009-01-01T00:00:00Z http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43980 標題: 高速記憶體模組之信號完整度分析與補償設計; Signal Integrity Analysis and Compensation Design of High Speed Memory Module 作者: Yu-Ning Wang; 王佑甯 摘要: 記憶體模組在現代電腦裡為一項不可缺少的產品；工作頻率更快以及體積的迷你化更是現代人所追求的。為了達到這些目標，記憶體模組內部晶片連線與電源系統之電磁效應影響在電腦設計時也相對地需要被審慎考慮。 本篇論文主要分為兩個部分，第一部分首先針對記憶體模組內不同工作區塊，指令/位址線(command/address line)與資料線(data line)，建立了單端信號線傳輸路徑上各個不連續結構的等效電路模型並將其串連起來，透過此分段化之模型，可了解各段不連續結構對於信號完整度的影響，同時利用實驗量測來驗證此模型的準確性。藉由建立電源和信號完整度的共同模擬環境，並整合了主動電路元件模型，也可瞭解到電源雜訊的影響。此方法也可應用在建立差模信號時序線的等效模型上，以此分析時序信號之信號完整度對取樣時間的影響。 第二部分則針對印刷電路板(PCB)上之非理想效應與構裝(package)結構作補償設計。PCB 上之非理想效應又主要可分三項：第一項為接地雜訊對信號連通柱造成的電感特性，利用增加連通柱的電容特性作補償；第二項為使用兩段不等長的傳輸線補償PCB走線分接連通柱長度不匹配的影響；第三項為差動信號線之飛越式(fly-by)佈線，提供一設計圖表可迅速地得到阻抗匹配所需之尺寸參數。而對於構裝結構，首先是指令/位址線之佈線重新配置，以期得到最小的等效電感值，與信號線間的串音效應，使信號完整度更理想。再來利用資料線構裝結構的等效電感值，配合其後主動電路的負載電容與傳輸線之特性阻抗作阻抗匹配。 總結以上對於高速記憶體模組的信號分析方法與補償設計，將有助於縮短業界硬體工程師的設計時程並使記憶體模組達到更有效率的應用。; Memory module has become a essential product in modern computer systems. People are always pursuing digital products with faster operating frequency and tiny volume. For achieving this goals, there are many things that should be considered carefully in computer design, for example, the chip connector in memory modules and the electro- magnetic problems in power systems. There are two parts in this thesis. In the first part, the equivalent models of all discontinuities along the single-ended transmission path is extracted and then linked together for different function blocks of memory module, i.e. command/address line and data line. By this divided model, the influence of each discontinuity on signal integrity can be evaluated. Also, the accuracy of each model is verified through experiments. By means of the construction of the co-simulation environment considering signal and power integrity, and also active circuit models, the ground noise issue can be discussed as well. Similarly, this method can be applied to help extract equivalent models of differential clock line. The influence of signal integrity of differential clock line on the variation of sampling time can then be analyzed. In the second part, it is all about the compensation design for the imperfect effects on PCB and package structure. There are three kinds of imperfect effects on PCB that need to be overcome. The first one is the overall inductive behavior of signal vias, which mainly comes from the induction of ground bounce noise. It can be compensated by increasing the capacitive loading of signal vias. For the second one, unbalanced transmission lines can be used to mitigate the influence of signal vias with unmatched lengths connecting the chip inputs. For the third one, a design curve is established to provide the required dimensions of transmission line for impedance matching design of differential fly-by layout. As for the package layout, smaller effective inductance and less crosstalk effect can be achieved through the reassignment of power/ground pins among all signal pins. With the above signal analysis methodology and compensation designs for high- speed memory module, it can help the engineers shorten the design process and make applications for memory module more efficiently. Thu, 01 Jan 2009 00:00:00 GMT http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43980 2009-01-01T00:00:00Z