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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉致為 | zh_TW |
| dc.contributor.advisor | Chee-Wee Liu | en |
| dc.contributor.author | 楊仁葳 | zh_TW |
| dc.contributor.author | Jen-Wei Yang | en |
| dc.date.accessioned | 2025-09-17T16:23:58Z | - |
| dc.date.available | 2025-09-18 | - |
| dc.date.copyright | 2025-09-17 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-04 | - |
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Domanski, "Latch-up in FinFET technologies," 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, USA, 2018, pp. 2C.4-1-2C.4-5, doi: 10.1109/IRPS.2018.8353550. [57] K. Serbulova et al., "Impact of Sub-µm Wafer Thinning on Latch-up Risk in STCO Scaling Era," 2021 43rd Annual EOS/ESD Symposium (EOS/ESD), Tucson, AZ, USA, 2021, pp. 1-6, doi: 10.23919/EOS/ESD52038.2021.9574787. [58] K. Serbulova et al., "Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO," 2023 45th Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2023, pp. 1-6, doi: 10.23919/EOS/ESD58195.2023.10287753. [59] G. Hiblot, K. Serbulova, G. Hellings and S. -H. Chen, "TCAD study of latch-up sensitivity to wafer thinning below 500 nm," 2021 International Semiconductor Conference (CAS), Romania, 2021, pp. 121-124, doi: 10.1109/CAS52836.2021.9604133. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99694 | - |
| dc.description.abstract | 本論文探討在先進製程節點下的設計與優化策略，並以功率（Power）、效能（Performance）、面積（Area）與成本（Cost），統稱為PPAC，作為評估基準。研究內容涵蓋新型電晶體堆疊架構設計、先進元件技術導入、電路層級之優化方法，以及基礎結構的改良，藉此深入分析性能強化的可行途徑。
本論文內容可區分為兩大部分。在第一部分中，提出一種基於互補式場效電晶體（Complementary FET, CFET）技術之新型10電晶體3端口（10T3P）靜態隨機存取記憶體（SRAM）單元。該架構針對記憶體內運算（Compute-In-Memory, CIM）應用所設計，旨在於記憶體陣列中直接執行計算操作，以有效緩解資料傳輸瓶頸，並降低系統延遲與能耗。本研究針對該10T3P SRAM單元的讀取延遲與能量消耗進行了全面分析，並根據結果進行有針對性的電路層級優化。與傳統8電晶體2端口（8T2P）SRAM架構相比，所提架構於讀取延遲與能量效率方面均展現顯著改善，顯示其於高效能CIM應用中的高度潛力。 第二部分則聚焦於針對N14與N3節點鰭式電晶體（FinFET）所進行的結構性優化。本研究提出在源極／汲極（Source/Drain, S/D）區域下方導入部分汲極隔離層（Partial Drain Isolation）之設計，以提升元件整體性能。模擬結果顯示，該結構性改良可顯著強化多項關鍵元件參數，包括直流與交流（DC/AC）電性特徵、SRAM操作速度（讀寫延遲），以及閂鎖效應（Latch-up Effect）之耐受性，進一步驗證其於先進製程節點下的實用價值。 | zh_TW |
| dc.description.abstract | This thesis presents design and optimization methodologies for advanced technology nodes, benchmarked against the primary industry metrics of Power, Performance, Area, and Cost (PPAC). The research investigates performance enhancement through the application of novel device architectures, advanced circuit-level strategies, and fundamental structural modifications.
The first part of this work introduces a novel 10-transistor, 3-port (10T3P) SRAM cell based on Complementary Field-Effect Transistor (CFET) technology, specifically engineered for Compute-In-Memory (CIM) applications. CIM is a paradigm that mitigates the data transfer bottleneck by executing computation directly within the memory array, thus reducing latency and power consumption. This research systematically analyzes the 10T3P cell's read delay and energy consumption, leading to the implementation of targeted optimization strategies. The resulting architecture demonstrates a significant reduction in read latency and energy consumption relative to a conventional 8-transistor, 2-port (8T2P) SRAM baseline, establishing its strong potential for high-performance CIM applications. In the second part, this thesis investigates a structural modification to N14 and N3 FinFETs by integrating a partial drain isolation layer beneath the source/drain (S/D) region. This architectural enhancement is shown to yield improvements in key device metrics, including DC/AC electrical characteristics, SRAM operational speed, and overall latch-up immunity. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-09-17T16:23:58Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-09-17T16:23:58Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 致謝 i
Related Publications (相關論文發表) ii Journal Papers (學術期刊論文) ii 摘要 iii ABSTRACT iv CONTENTS vi List of Figures viii List of Tables xi Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Thesis Organization 6 Chapter 2 10T3P SRAM with Transient and Power Analysis 8 2.1 Introduction 8 2.2 Architecture of 10T3P CFET SRAM and MAC Logic 11 2.3 Read Delay and Power Analysis 13 2.4 Summary 17 Chapter 3 DTCO for Read Delay Reduction in 10T3P SRAM 18 3.1 Introduction 18 3.2 Dual Rail Design and HVT Devices 18 3.3 Layout Optimization 23 3.4 Summary 25 Chapter 4 N14/N3 FinFET SRAM Transient Analysis and Latch-up Immunity 27 4.1 Introduction 27 4.2 Architecture of FinFET SRAM with Partial Drain Isolation 29 4.3 SRAM Transient Analysis 34 4.4 Latch-up Effect and Beta Gain 40 4.5 Summary 44 Chapter 5 Summary 45 5.1 Summary 45 5.2 Future Works 46 REFERENCE 47 | - |
| dc.language.iso | en | - |
| dc.subject | 靜態隨機存取記憶體 | zh_TW |
| dc.subject | 設計技術協同優化 | zh_TW |
| dc.subject | 互補式場效電晶體 | zh_TW |
| dc.subject | 記憶體內運算 | zh_TW |
| dc.subject | 鰭式電晶體 | zh_TW |
| dc.subject | 部分汲極隔離層 | zh_TW |
| dc.subject | 閂鎖效應 | zh_TW |
| dc.subject | Design-Technology Co-Optimization | en |
| dc.subject | latch-up effect | en |
| dc.subject | partial drain isolation | en |
| dc.subject | FinFET | en |
| dc.subject | Compute-In-Memory | en |
| dc.subject | Complementary Field-Effect Transistor | en |
| dc.subject | static random-access memory | en |
| dc.title | 先進製程靜態隨機存取記憶體設計、優化與可靠性研究 | zh_TW |
| dc.title | Design, Optimization, and Reliability Analysis of SRAM in Advanced Technology | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李敏鴻;林楚軒;林中一 | zh_TW |
| dc.contributor.oralexamcommittee | Min-Hung Lee;Chu-Hsuan Lin;Chung-Yi Lin | en |
| dc.subject.keyword | 靜態隨機存取記憶體,設計技術協同優化,互補式場效電晶體,記憶體內運算,鰭式電晶體,部分汲極隔離層,閂鎖效應, | zh_TW |
| dc.subject.keyword | static random-access memory,Design-Technology Co-Optimization,Complementary Field-Effect Transistor,Compute-In-Memory,FinFET,partial drain isolation,latch-up effect, | en |
| dc.relation.page | 55 | - |
| dc.identifier.doi | 10.6342/NTU202503745 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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