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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
Please use this identifier to cite or link to this item: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99683
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???org.dspace.app.webui.jsptag.ItemTag.dcfield???ValueLanguage
dc.contributor.advisor陳中平zh_TW
dc.contributor.advisorCharlie Chung-Ping Chenen
dc.contributor.author吳宗翰zh_TW
dc.contributor.authorTSUNG-HAN WUen
dc.date.accessioned2025-09-17T16:21:58Z-
dc.date.available2025-09-18-
dc.date.copyright2025-09-17-
dc.date.issued2025-
dc.date.submitted2025-07-21-
dc.identifier.citationA. CoWoS
[1] S. P. Jeng and M. Liu, "Heterogeneous and Chiplet Integration Using Organic Interposer (CoWoS-R)," 2022 International Electron Devices Meeting (IEDM), San Francisco, USA, pp. 3.2.1-3.2.4, 2022.
[2] Y. C. Hu, Y. M. Liang, H. P. Hu, C. Y. Tan, C. T. Shen, C. H. Lee and S. Y. Hou, "CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1022-1026, 2023.
[3] M. S. Lin, T. C. Huang, C. C. Tsai, K. H. Tam, K. C. H. Hsieh, C. F. Chen, W. H. Huang, C. W. Hu, Y. C. Chen, S. K. Goel, C. M. Fu, S. Rusu, C. C. Li, S. Y. Yang, M. Wong, S. C. Yang and F. Lee, "A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 956-966, 2020.
[4] P. K. Huang, C. Y. Lu, W. H. Wei, C. Chiu, K. C. Ting, C. Hu, C. H. Tsai, S. Y. Hou, W. C. Chiou, C. T. Wang, and D. Yu , "Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 101-104, 2021.
[5] W. C. Chen, C. Hu, K. C. Ting, V. Wei, T. H. Yu, S. Y. Huang, V. C. Y. Chang, C. T. Wang, S. Y. Hou, C. H. Wu and D. Yu, "Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology," in IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4071-4077, 2017.
[6] S. K. Goel, S. Adham, M. J. Wang, J. J. Chen, T. C. Huang, A. Mehta, F. Lee, V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, J. Cho, H. H. Lee, J. Choi and S. Kim, "Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study," 2013 IEEE International Test Conference (ITC), Anaheim, USA, pp. 1-10, 2013.
[7] P. Y. Lin, M. C. Yew, S. S. Yeh, S. M. Chen, C. H. Lin, C. S. Chen, C. C. Hsieh, Y. J. Lu, P. Y. Chuang, H. K. Cheng and S. P. Jeng, "Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 723-728, 2021.
[8] L. Lin, T. C. Yeh, J. L. Wu, G. Lu, T. F. Tsai, L. Chen and A. T. Xu, "Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology," 2013 IEEE 63rd Electronic Components and Technology Conference, Las Vegas, USA, pp. 366-371, 2013.
B. InFO
[9] C. F. Tseng, C. S. Liu, C. H. Wu and D. Yu, "InFO (Wafer Level Integrated Fan-Out) Technology," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 1-6, 2016.
[10] C. T. Wang and D. Yu, "Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 380-385, 2016.
[11] H. P. Pu, H. J. Kuo, C. S. Liu and D. C. H. Yu, "A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO Packaging," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 45-51, 2018.
[12] T. Ko, H. P. Pu, Y. Chiang, H. J. Kuo, C. T. Wang, C. S. Liu and D. C. H. Yu, "Applications and Reliability Study of InFO_UHD (Ultra-High-Density) Technology," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1120-1125, 2020.
[13] S. R. Chun, T. H. Kuo, H. Y. Tsai, C. S. Liu, C. T. Wang, J. S. Hsieh, T. S. Lin, T. Ku and D. Yu, "InFO_SoW (System-on-Wafer) for High Performance Computing," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1-6, 2020.
[14] Y. P. Chiang, S. P. Tai, W. C. Wu, J. Yeh, C. T. Wang and D. C. H. Yu, "InFO_oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet Integration," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 130-135, 2021.
[15] C. T. Wang, T. C. Tang, C. W. Lin, C. W. Hsu, J. S. Hsieh, C. H. Tsai, K. C. Wu, H. P. Pu and D. Yu, "InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration," 2018 IEEE 68th Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 202-207, 2018.
[16] C. W. Hsu, C. H. Tsai, J. S. Hsieh, K. C. Yee, C. T. Wang and D. Yu, "High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL," 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 254-259, 2017.
[17] C. T. Wang and D. Yu, "Power-Performance Advantages of InFO Technology for Advanced System Integration," 2019 International 3D Systems Integration Conference (3DIC), Sendai, Japan, pp. 1-4, 2019.
[18] C. H. Hsu, Y. J. Lin, S. L. Kuo, Y. H. Peng, C. W. Pan, T. Y. Chen and W. S. Hsu, "Thermal Characteristics of Integrated Fan-Out on Substrate (InFO_oS) Packaging Technology," 2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), Orlando, USA, pp. 212-218, 2020.
C. SoIC
[19] C. C. Hu, M. F. Chen, W. C. Chiou and D. C. H. Yu, "3D Multi-chip Integration with System on Integrated Chips (SoIC™)," 2019 Symposium on VLSI Technology, Kyoto, Japan, pp. T20-T21, 2019.
[20] S. W. Liang, G. C. Y. Wu, K. C. Yee, C. T. Wang, J. J. Cui and D. C. H. Yu, "High Performance and Energy Efficient Computing with Advanced SoIC™ Scaling," 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, USA, pp. 1090-1094, 2022.
[21] C. H. Tsai, T. Ku, M. F. Chen, W. C. Chiou, C. T. Wang and D. Yu, "Low Temperature SoIC™ Bonding and Stacking Technology for 12/16-Hi High Bandwidth Memory (HBM)," 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, pp. 1-2, 2020.
[22] M. F. Chen, C. S. Lin, E. B. Liao, W. C. Chiou, C. C. Kuo, C. C. Hu, C. H. Tsai, C. T. Wang and D. Yu, "SoIC for Low-Temperature, Multi-Layer 3D Memory Integration," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 855-860, 2020.
[23] D. C. H. Yu, C. T. Wang, C. C. Lin, C. H. Lu, G. Wu, C. Y. Huang, W. T. Chen, T. Ku, K. C. Yee and C. H. Tsai, "SoIC_H Technology for Heterogeneous System Integration," in IEEE Transactions on Electron Devices, vol. 69, no. 12, pp. 7167-7172, 2022.
[24] M. F. Chen, F. C. Chen, W. C. Chiou and D. C. H. Yu, "System on Integrated Chips (SoIC(TM) for 3D Heterogeneous Integration," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, USA, pp. 594-599, 2019.
[25] H. J. Chia, S. P. Tai, J. J. Cui, C. T. Wang, C. H. Tung, K. C. Yee and D. C. H. Yu, "Ultra High Density Low Temperature SoIC with Sub-0.5 μm Bond Pitch," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 1-4, 2023.
[26] Y. H. Chen, C. A. Yang, C. C. Kuo, M. F. Chen, C. H. Tung, W. C. Chiou and D. Yu, "Ultra High Density SoIC with Sub-micron Bond Pitch," 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), Orlando, USA, pp. 576-581, 2020.
D. Thermal Issue
[27] Y. L. Shen, "Analysis of Joule heating in multilevel interconnects," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, , vol. 17, pp. 2115-2121, 1999.
[28] K. W. Yan, P. Y. Lin and S. L. Kuo, "Thermal Challenges for HPC 3DFabricTM Packages and Systems," 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas, USA, pp. 4C.1-1-4C.1-6, 2022.
[29] K. Yan, P. Y. Lin and S. L. Kuo, "Thermal Challenges for HPC 3DIC Packages and Systems," 2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Oita, Japan, pp. 151-153, 2022.
[30] B. Bai, S. Chen, W. Wang, H. Hao and L. Li, "Thermal management of integrated circuits in burn-in environment," The Proceedings of 2011 9th International Conference on Reliability, Maintainability and Safety, Guiyang, China, pp. 1092-1095, 2011.
[31] S. Shi, X. Zhang and R. Luo, "The thermal-aware floorplanning for 3D ICs using Carbon Nanotube," 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 1155-1158, 2010.
[32] A. L. Moore and Li Shi, "Emerging challenges and materials for thermal management of electronics," Materials Today, vol. 17, pp. 163-174, 2014.
[33] S. P. Gurrum, S. K. Suman, Y. K. Joshi and A. G. Fedorov, "Thermal issues in next-generation integrated circuits," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 4, pp. 709-714, 2004.
[34] F. Tavakkoli, S. Ebrahimi, S. Wang, K. Vafai, "Analysis of critical thermal issues in 3D integrated circuits," International Journal of Heat and Mass Transfer, vol. 97, pp. 337-352, 2016.
E. Thermal Modeling and Simulation Techniques
[35] Peng Li, L. T. Pileggi, M. Asheghi and R. Chandra, "Efficient full-chip thermal modeling and analysis," IEEE/ACM International Conference on Computer Aided Design, 2004. (ICCAD), San Jose, USA, pp. 319-326, 2004.
[36] M. Pedram and S. Nazarian, "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods," Proceedings of the IEEE, vol. 94, no. 8, pp. 1487-1501, 2006.
[37] A. Jain, R. E. Jones, Ritwik Chatterjee, S. Pozder and Zhihong Huang, "Thermal modeling and design of 3D integrated circuits," 2008 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Orlando, USA, pp. 1139-1145, 2008.
[38] Sungjun Im and K. Banerjee, "Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs," International Electron Devices Meeting 2000. Technical Digest. (IEDM), San Francisco, USA, pp. 727-730, 2000.
[39] Z. Cao, J. Li, J. Tao and Y. Chen, "3D Compact Thermal Model and its Application on Fast Chip Level Thermal Simulation," 2023 International Symposium of Electronics Design Automation (ISEDA), Nanjing, China, pp. 246-249, 2023.
[40] A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler and D. Atienza, "3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling," 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 463-470, 2010.
[41] M. N. Ozisik, "Finite Difference Methods in Heat Transfer," New York:CRC, 1994.
[42] Wei Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron and M. R. Stan, "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 501-513, 2006.
[43] T. Y. Wang and Charlie C. P. Chen, "3-D Thermal-ADI: a linear-time chip level transient thermal simulator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (ICCAD), vol. 21, no. 12, pp. 1434-1445, 2002.
[44] J. Li, M. Tang and J. Mao, "An Efficient ADI Method for Transient Thermal Simulation of Liquid-Cooled 3-D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 9, pp. 1484-1491, 2022.
[45] R. W. Lewis, P. Nithiarasu, K. N. Seetharamu, "Fundamentals of the Finite Element Method for Heat and Fluid Flow," Wiley, 2004.
[46] B. Li, M. Tang, Y. Zhi and H. Yu, "Thermal Simulation of 3-D Stacked Integrated Circuits with Layered Finite Element Method," 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall), Xiamen, China, pp. 1883-1886, 2019.
[47] B. Li, M. Tang, P. Li and J. Mao, "Efficient Thermal Analysis of Integrated Circuits and Packages With Microchannel Cooling Using Laguerre-Based Layered Finite Element Method," IEEE Journal on Multiscale and Multiphysics Computational Techniques, vol. 8, pp. 195-204, 2023.
[48] D. Oh, C. C. P. Chen and Y. H. Hu, "Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 11, pp. 1767-1771, 2012.
[49] L. Codecasa, V. d'Alessandro, A. Magnani, N. Rinaldi and P. J. Zampardi, "Fast novel thermal analysis simulation tool for integrated circuits (FANTASTIC)," 20th International Workshop on Thermal Investigations of ICs and Systems, Greenwich, UK, 2014, pp. 1-6.
[50] Ansys, "Ansys Collaborates with TSMC to Deliver Thermal Analysis Solution for 3D IC Designs," https://www.ansys.com/en-in/news-center/press-releases/10-27-21-ansys-collaborates-with-tsmc-to-deliver-thermal-analysis-solution-for-3d-ic-designs, 2021.
[51] M. Roshandell, "Successful Thermal Management of 3D-ICs: Accurate, Fast, Efficient and Scalable with Celsius," https://community.cadence.com/cadence_blogs_8/b/pcb/posts/successful-thermal-management-of-3d_2d00_ics, 2022.
[52] Z. Tokei, H. Oprins, M. Lofrano, and X. Chang, "Mitigating the thermal bottleneck in advanced interconnects," Chip Scale Review, vol. 27, pp. 43-48, 2023.
F. Finite Element Method Implementation
[53] S. K. Jeng, "Finite Element Method 2D: Rectangle Bases," Unpublished internal presentation, 2024.
[54] KC, G., & Dulal, R. P., "Adaptive Finite Element Method for Solving Poisson Partial Differential Equation," Journal of Nepal Mathematical Society, vol. 4, no. 1, pp. 1–18, 2021.
[55] S. K. Jeng, " Boundary Condition Errors and Profiling," Unpublished internal presentation, 2024.
G. Physics Informed Neural Network
[56] Raissi, M., Perdikaris, P., & Karniadakis, G. E. (2019). Physics-informed neural networks: A deep learning framework for solving forward and inverse problems involving nonlinear partial differential equations. Journal of Computational physics, 378, 686-707.
[57] Bafghi, R. A., & Raissi, M. (2023). PINNs-Torch: Enhancing Speed and Usability of Physics-Informed Neural Networks with PyTorch. In The Symbiosis of Deep Learning and Differential Equations III..
[58] Rathore, P., Lei, W., Frangella, Z., Lu, L., & Udell, M. (2024). Challenges in training PINNs: A loss landscape perspective. arXiv preprint arXiv:2402.01868.
[59] Gao, H., Zuo, W., Feng, Z., Yang, J., Li, T., & Hu, P. (2022). DHEM: a deep heat energy method for steady-state heat conduction problems. Journal of Mechanical Science and Technology, 36(11), 5777-5791.
[60] Wang, X., Yin, Z. Y., Wu, W., & Zhu, H. H. (2025). Neural network-augmented differentiable finite element method for boundary value problems. International Journal of Mechanical Sciences, 285, 109783.
[61] Wu, C., Zhu, M., Tan, Q., Kartha, Y., & Lu, L. (2023). A comprehensive study of non-adaptive and residual-based adaptive sampling for physics-informed neural networks. Computer Methods in Applied Mechanics and Engineering, 403, 115671.
[62] NVIDIA Corporation. (2022). NVIDIA Modulus – User Guide: Advanced PINN Schemes. Retrieved May 5, 2025, from https://docs.nvidia.com/deeplearning/modulus/modulusv2209/user_guide/theory/advanced_schemes.html
[63] Wang, S., Li, B., Chen, Y., & Perdikaris, P. (2024). PirateNets: Physics-informed deep learning with residual adaptive networks. arXiv preprint arXiv:2402.00326. https://doi.org/10.48550/arXiv.2402.00326
[64] Gao, Z., Yan, L., & Zhou, T. (2022). Failure-informed adaptive sampling for PINNs. SIAM J. Sci. Comput., 45, 1971-. https://doi.org/10.48550/arXiv.2210.00279.
[65] Anticev, J., Aghdaei, A., Cheng, W., & Feng, Z. (2024). SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks. , 277:1-277:6. https://doi.org/10.48550/arXiv.2407.07358.
[66] Anticev, J., Aghdaei, A., Cheng, W., & Feng, Z. (2024). SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks. , 277:1-277:6. https://doi.org/10.48550/arXiv.2407.07358.
[67] Nabian, M., Gladstone, R., & Meidani, H. (2021). Efficient training of physics‐informed neural networks via importance sampling. Computer‐Aided Civil and Infrastructure Engineering, 36, 962 - 977. https://doi.org/10.1111/mice.12685.
H. Neural Network Architecture
[68] He, K., Zhang, X., Ren, S., & Sun, J. (2016). Deep residual learning for image recognition. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (pp. 770–778). https://doi.org/10.1109/CVPR.2016.90
[69] Liu, Z., Cai, W., & Xu, Z.-Q. J. (2020). Multi-scale deep neural network (MscaleDNN) for solving Poisson–Boltzmann equation in complex domains. Communications in Computational Physics, 28(5), 1970–2001. https://doi.org/10.4208/cicp.OA-2020-0179
[70] Eshkofti, K., & Hosseini, S. (2024). A new modified deep learning technique based on physics-informed neural networks (PINNs) for the shock-induced coupled thermoelasticity analysis in a porous material. Journal of Thermal Stresses, 47, 798 - 825. https://doi.org/10.1080/01495739.2024.2321205.
[71] Yu, M., Long, X., Jiang, C., & Ouyang, Z. (2024). Physics-informed neural networks for V-notch stress intensity factor calculation. Theoretical and Applied Fracture Mechanics. https://doi.org/10.1016/j.tafmec.2024.104717.
[72] S. K. Jeng, "PINN2D Solution with Normalization and Boundary Condition Enforcement," Unpublished internal presentation, 2025.
I. Domain Decomposition Method
[73] Y. –C. Chen (2025), Domain Decomposition Method for Steady-State Thermal Analysis with Multiscale Technique, Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/99683-
dc.description.abstract隨著積體電路封裝與功率密度的快速提升,精確且高效的熱傳導數值模擬成為現代半導體設計中的一大挑戰。傳統有限元素法(FEM)雖能提供高精度,但在多維度、高解析度問題下計算成本高昂。物理資訊神經網路(PINN)作為一種新興自動微分模型,能夠直接將偏微分方程融入網路訓練,無需網格化生成即可求解熱傳導問題,然而其訓練過程常因殘差不平衡與採樣效率低下而導致收斂緩慢、精度不足。
本論文提出一種「粗網路到細網路」的混合 PINN 解法:
1. 粗網路預訓練:訓練一個小型(隱藏層較少) PINN,以快速擬合初步解形態。
2. 遷移學習初始化:將粗網路的參數部分轉移至更高容量的細網路(隱藏層較多)中,並添加微量噪聲以提高模型魯棒性。
3. 二階段自適應訓練:在 Phase A 凝聚頂層參數,快速優化結構層;Phase B 全參數解凍結合改進的自適應採樣算法(結合誤差與梯度權重),動態引入新樣本以聚焦高誤差區域。
4. 混合精度與自動釋放:全程採用 CUDA AMP 自動混合精度,並在自適應採樣後主動調用減少 GPU 記憶體占用。
5. 以二維二次分佈熱源問題為例,與解析解比較結果顯示,在相同訓練步數下,細網路透過遷移學習與自適應採樣,可將相對 L₂ 誤差從 1e-2 降至 1e-4。
6. 相較於單一 PINN,總訓練時間縮短約 40%;收斂曲線更平滑穩定,實驗結果支持本方法在高精度熱模擬任務中的可行性與優勢。
本研究所提出的混合 PINN 框架兼具效率與精度,並具備良好的模組化設計,可延伸至其他高階偏微分方程或是其他物理問題求解。
zh_TW
dc.description.abstractWith the rapid increase in power density and packaging complexity of integrated circuits, accurate yet efficient thermal simulation has become a critical challenge in modern semiconductor design. While the Finite Element Method (FEM) achieves high accuracy, its computational cost escalates sharply for multidimensional, high-resolution problems. Physics-Informed Neural Networks (PINN) offer a mesh-free alternative by embedding partial differential equations directly into the network’s loss function via automatic differentiation. However, PINN often suffer from slow convergence and limited accuracy due to unbalanced residual terms and inefficient sampling strategies.
This thesis presents a coarse-to-fine hybrid PINN framework to accelerate convergence and enhance solution accuracy:
1. Coarse PINN Pretraining: Two lightweight PINNs are trained separately to approximate the homogeneous and particular solutions, capturing the dominant features of the heat transfer field.
2. Transfer Learning Initialization: Selected layers of the coarse networks are transferred into a higher-capacity fine PINN, with small Gaussian perturbations added for robustness.
3. Two-Phase Adaptive Training: Phase A: Freeze shared layers and optimize only the newly initialized layers to rapidly align solution scales. Phase B: Unfreeze all parameters and employ an improved adaptive sampling algorithm—combining K-Means clustering with a weighted error gradient criterion to dynamically introduce new collocation points in regions of high residual.
4. Mixed-Precision and Memory Management: Leverage CUDA Automatic Mixed Precision throughout training after each adaptive sampling step to reduce GPU memory footprint.
5. For a 2D quadratic heat source problem, comparisons against the analytic solution demonstrate that, at equal training iterations: The fine PINN with transfer learning and adaptive sampling reduces L₂ error from 1e-2 to 1e-4.
6. Overall training time is decreased by ~40%, and GPU memory usage is cut by ~30% compared to a baseline PINN. The convergence curves exhibit markedly smoother and more stable behavior.
The hybrid PINN framework proposed in this study combines both efficiency and accuracy, and its modular design allows it to be extended to other higher-order partial differential equations or to solve different physical problems.
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dc.description.tableofcontents致謝 I
中文摘要 III
ABSTRACT IV
LIST OF CONTENTS VI
LIST OF FIGURES XI
LIST OF TABLES XIII
LIST OF SYMBOLS XIII
LIST OF ABBREVIATIONS XV
CHAPTER 1 1
1.1 Research Background and Motivation 1
1.1.1 Industrial demands for 2D/3D heat-transfer simulation 1
1.1.2 Opportunities and challenges of PINNs in physics-based modeling 2
1.2 Literature Review 3
1.2.1 Advanced Packaging and Chip Stacking Techniques 3
1.2.2 Classical Numerical Methods 5
1.2.3 Fundamentals of Physics-Informed Neural Networks 6
1.2.4 Extensions of PINNs for Thermal Problems 7
1.2.5 Sampling Strategy 8
1.2.6 Advances in Network Architectures and Applications 9
1.2.7 Boundary Enforcement via Analytical Lifting and Normalization 10
1.3 Contributions and Thesis Organization 10
CHAPTER 2 12
2.1 Governing Equations for Heat Conduction 12
2.1.1 Conservation of Energy 12
2.1.2 Fourier’s Law of Heat Conduction 12
2.1.3 Initial and Boundary Conditions 13
2.2 Physics-Informed Neural Networks 14
2.2.1 PINN Framework Overview 14
2.2.2 Loss Function Formulation and Multi-Task Optimization 15
2.2.3 Adaptive Sampling and Loss Weighting Techniques 15
CHAPTER 3 17
3.1 Neural Network Architecture 17
3.1.1 Residual Connections and Multi-Scale Branching 17
3.2 Construction of the Loss Function 19
3.2.1 PDE Residual Term 19
3.2.2 Boundary/Initial Condition Terms 19
3.2.3 Dynamic Weighting and Gradient Normalization 20
3.3 Non-Dimensionalization and Input Scaling 21
3.3.1 Non-Dimensionalization Procedure 21
3.3.2 Variable Standardization Strategies 21
3.3.3 Boundary Condition Assessment 22
3.4 Coarse-to-Fine Transfer Learning via Weight Mapping 23
3.4.1 Coarse PINN Pretraining 23
3.4.2 Layer Correspondence and State-Dict Mapping 23
3.4.3 Noise Injection for Robust Initialization 24
3.5 Proposed PINN Architecture 25
CHAPTER 4 28
4.1 Software Framework and Libraries 28
4.1.1 Integration with PyTorch Lightning 28
4.1.2 Mixed-Precision Training with CUDA AMP 28
4.2 Adaptive Sampling Algorithm 29
4.2.1 Residual-Based Refinement 29
4.2.2 K-Means Clustering for Point Selection 30
4.2.3 Score Function Construction and Tree-Based Sampling 32
4.2.4 Corner Aware Sampling 38
4.2.5 Enhanced Score Function for Heat‐Flux–Driven Sampling 41
4.3 Training Strategies 42
4.3.1 Two-Stage Optimization: Adam Followed by L-BFGS 42
4.3.2 Learning Rate Scheduling 42
4.3.3 Gradient Accumulation and Checkpointing 43
CHAPTER 5 44
5.1 Experiment Setup and Evaluation Metrics 44
5.1.1 Computational Environment 44
5.1.2 Test Cases and Boundary Conditions 44
5.2 Accuracy and Convergence Analysis 46
5.2.1 Comparison with Analytical Solutions 46
5.2.2 Convergence Curves and Sensitivity Study 48
5.2.3 Effect of Adaptive Sampling 53
5.3 Ablation Studies 56
5.3.1 Impact of Mixed-Precision Training 56
5.3.2 Comparison of Sampling Strategies 58
5.4 Performance Metrics: Training Time and Memory Usage 63
5.5 Verification of Heat‑Flux‑Driven Adaptive Sampling 71
CHAPTER 6 74
6.1 Summary of Findings 74
6.2 Limitations of the Current Study 75
6.3 Directions for Future Research 76
REFERENCES 79
A. CoWoS 79
B. InFO 81
C. SoIC 83
D. Thermal Issue 85
E. Thermal Modeling and Simulation Techniques 86
F. Finite Element Method Implementation 89
G. Physics Informed Neural Network 90
H. Neural Network Architecture 92
I. Domain Decomposition Method 93
-
dc.language.isoen-
dc.subject自適應採樣方法zh_TW
dc.subject物理資訊神經網路zh_TW
dc.subject先進封裝zh_TW
dc.subject三維積體電路zh_TW
dc.subject熱分析zh_TW
dc.subjectPhysics Informed Neural Networken
dc.subjectAdaptive Sampling Methoden
dc.subjectAdvanced Packagingen
dc.subject3D ICen
dc.subjectThermal Analysisen
dc.title基於強制物理資訊神經網路之熱分析:結合遷移學習與自適應取樣zh_TW
dc.titleThermal Analysis Based on Enforced Physics Informed Neural Network with Transfer Learning and Adaptive Samplingen
dc.typeThesis-
dc.date.schoolyear113-2-
dc.description.degree碩士-
dc.contributor.coadvisor鄭士康zh_TW
dc.contributor.coadvisorShyh-Kang Jengen
dc.contributor.oralexamcommittee陳柏羽zh_TW
dc.contributor.oralexamcommitteePo-Yu Chenen
dc.subject.keyword物理資訊神經網路,自適應採樣方法,熱分析,三維積體電路,先進封裝,zh_TW
dc.subject.keywordPhysics Informed Neural Network,Adaptive Sampling Method,Thermal Analysis,3D IC,Advanced Packaging,en
dc.relation.page93-
dc.identifier.doi10.6342/NTU202502085-
dc.rights.note未授權-
dc.date.accepted2025-07-22-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
dc.date.embargo-liftN/A-
Appears in Collections:電子工程學研究所

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