考慮非整數倍數高度之標準元件之平行化電路節點重映射

Abstract

當前超大型積體電路 (very-large scale integration, VLSI) 快速提升的複雜度，以及包含非整數倍數高度（non-integer multiple-cell-height, NIMCH）之標準元件的設計，對時序感知電路節點重映射 (remapping) 帶來新的挑戰。現有的重映射流程在處理所有電路節點與邏輯閘對應組合時需進行全面列舉，並依賴序列式動態規劃 (dynamic programming) 演算法，導致運算開銷龐大。為了解決上述效率問題，我們提出一種創新的考慮非整數倍數高度之標準元件 (standard cell) 之電路節點重映射演算法，包含以下兩項策略：平行化最長路徑優先策略以及迭代最小時序裕量 (slack) 優先策略。這兩種策略皆優先處理時序關鍵電路節點，以加速整體流程。其中，最長路徑優先策略允許平行運算，顯著提升重映射速度。實驗結果顯示，與現有最先進方法相比，我們的方法平均可達到 8.92 倍的執行速度提升，同時維持相同的布局品質。本流程的效率與可擴展性大幅提升，使其非常適合應用於需快速達成時序收斂的大規模實體設計中。

The fast-growing complexity of VLSI circuits with non-integer multiple-cell-height (NIMCH) standard cells poses new challenges for timing-aware node remapping. The existing remapping flow suffers from significant computational overhead due to exhaustive enumeration of all node-to-gate mapping combinations and the sequential dynamic programming algorithm. To remedy this inefficiency, we propose a novel NIMCH node remapping flow consisting of the following two schemes: a parallel longest-path-first scheme and an iterative minimum-slack-first scheme. Both schemes prioritize timing-critical nodes to reduce runtime. Moreover, the longest-path-first scheme enables parallel execution, substantially accelerating the remapping process. Experimental results show that our proposed method achieves an average runtime speedup of 8.92X compared to the state-of-the-art approach, while preserving placement quality. The improved efficiency and scalability of our flow make it well-suited for large-scale physical design applications where rapid timing closure is essential.