請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98938完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢 | zh_TW |
| dc.contributor.advisor | Tsung-Hsien Lin | en |
| dc.contributor.author | 劉家均 | zh_TW |
| dc.contributor.author | Chia-Chun Liu | en |
| dc.date.accessioned | 2025-08-20T16:21:39Z | - |
| dc.date.available | 2025-08-21 | - |
| dc.date.copyright | 2025-08-20 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-14 | - |
| dc.identifier.citation | [1] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, "Internet of Things (IoT): A Vision, Architectural Elements, and Future Directions," Future Generation. Comput. Syst., vol. 29, no. 7, pp. 1645-1660, Jul. 2013.
[2] A. Nikoukar, S. Raza, A. Poole, M. Güneş and B. Dezfouli, "Low-Power Wireless for the Internet of Things: Standards and Applications," IEEE Access, vol. 6, pp. 67893-67926, Nov. 2018. [3] R. Schreier and G. C. Temes, "Understanding Delta-Sigma Data Converters," Wiley, 2005. [4] R. Schreier, J. Silva, J. Steensgaard and G. C. Temes, "Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2358-2368, Nov. 2005. [5] C.-A. Gobet and A. Knob, "Noise Analysis of Switched-Capacitor Networks," IEEE Transactions on Circuits and Systems, vol. 30, no. 1, pp. 37-43, Jan. 1983. [6] S.-H. Liao and J.-T. Wu, "A 1-V 175-μW 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques," IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2523-2531, Sep. 2019. [7] W.-C. Lai, J.-F. Huang, C.-L. Wen and W.-T. Lay, "FPGA implementation of a MASH 1-1-1 delta-sigma modulator infractional-N phase locked loop for fuzzy control application," 11th International Conference on Fuzzy Systems and Knowledge Discovery (FSKD), Xiamen, China, pp. 131-134, 2014. [8] Y. Hu, Y. Zhao, W. Qu, L. Ye, M. Zhao and Z. Tan, "A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 410-412, 2022. [9] T. He, M. Kareppagoudr, Y. Zhang, E. Caceres, U.-K. Moon and G. C. Temes, "Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1331-1341, Apr. 2019. [10] C. Y. Lee, P. K. Venkatachala, A. ElShater and U.-K. Moon, "A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 7, pp. 2327-2331, Jul. 2021. [11] Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata and R. Schreier, "15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 278-279, 2016. [12] C. Kim, S. Joshi, H. Courellis, J. Wang, C. Miller and G. Cauwenberghs, "Sub-u Vrms-Noise Sub- uW/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging," IEEE Journal of Solid-State Circuits, vol. 53, no. 11, pp. 3101-3110, Nov. 2018. [13] H.-Y. Lee, P.-W. Huang, D.-S. Ciou, Z.-X. Liao and S.-Y. Lee, "A Power-Efficient Current Readout Circuit with VCO-Based 2nd-Order CT ΔΣ ADC for Electrochemistry Acquisition," IEEE Asian Solid-State Circuits Conference, pp. 1-2, 2020. [14] A. Nikas, S. Jambunathan, L. Klein, M. Voelker and M. Ortmanns, "A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording," IEEE Journal of Solid-State Circuits, vol. 54, no. 10, pp. 2879-2891, Oct. 2019. [15] H. Jeon, J.-S. Bang, Y. Jung, T. Lee, Y. Jeon and S.-T, Koh, "A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS," IEEE Asian Solid-State Circuits Conference, Tainan, Taiwan, pp. 91-92, 2018. [16] W. Wang, Y. Zhu, C.-H. Chan and R. P. Martins, "A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 53, no. 10, pp. 2783-2794, Oct. 2018. [17] B. Wu, S. Zhu, B. Xu and Y. Chiu, "A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR," IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2893-2905, Dec. 2016. [18] I.-H. Jang, M.-J. Seo, S.-H. Cho, J.-K. Lee, S.-Y. Baek and S. Kwon, "A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling," IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1139-1148, Apr. 2018. [19] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 42, no. 12, pp. 753-762, Dec. 1995. [20] T.-H. Kuo, K.-D. Chen and H.-R. Yeng, "A wideband CMOS sigma-delta modulator with incremental data weighted averaging," IEEE Journal of Solid-State Circuits, vol. 37, no. 1, pp. 11-17, Jan. 2002. [21] K.-D. Chen and T.-H. Kuo, "An improved technique for reducing baseband tones in sigma-delta modulators employing data weighted averaging algorithm without adding dither," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 1, pp. 63-68, Jan. 1999. [22] Y. Hu, Y. Zhao, W. Qu, L. Ye, M. Zhao and Z. Tan, "A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 410-412, 2022. [23] M. Fukazawa and T. Matsui, "A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer," IEEE Symposium on VLSI Technology and Circuits, Kyoto, Japan, pp. 1-2, 2023. [24] Y. H. Leow, H. Tang, Z. C. Sun and L. Siek, "A 1 V 103 dB 3rd-Order Audio Continuous-Time Delta Sigma ADC With Enhanced Noise Shaping in 65 nm CMOS," IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2625-2638, Nov. 2016. [25] S.-H. Wu, Y.-S. Shu, A. Y.-C. Chiou, W.-H. Huang, Z.-X. Chen and H.-Y. Hsieh, "9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 154-156, 2020. [26] R. S. A. Kumar, N. Krishnapura and P. Banerjee, "Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 3384-3395, Nov. 2022. [27] A. Matsuoka, T. Nezuka and T. Iizuka, "Fully Dynamic Discrete-Time ΔΣ ADC Using Closed-Loop Two-Stage Cascoded Floating Inverter Amplifiers," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 944-948, Mar. 2022. [28] B. Li, X. Jiang, G. Reynolds, S. Song, M. Chen and S. Wang, "A High Dynamic Range Hybrid CT/DT Delta-Sigma Modulator for Medical X-ray Imaging," IEEE Biomedical Circuits and Systems Conference, Xi'an, China, pp. 1-5, 2024. [29] H. Zhao, X. Zhang, Q. Deng, J. Hu, Z. Li and S. Yang, "18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMs in 1kHz BW," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 306-308, 2025. [30] S. Li, "A kT/C-Noise-Cancelled Noise-Shaping SAR ADC with a Duty-Cycled Amplifier," IEEE 63rd International Midwest Symposium on Circuits and Systems, pp. 758-761, Sep. 2020. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98938 | - |
| dc.description.abstract | 在現代物聯網(IoT)系統的應用中，高精度的類比數位轉換器(ADC)對於訊號的處理至關重要，影響著整體系統的性能表現。本篇論文將提出兩種不同架構的類比數位轉換器設計，以滿足物聯網設備對於高效能與低功耗的需求。
晶片一為一離散時間之三角積分調變器，以多級雜訊整形(Multi Stage Noise Shaping)來實現高階雜訊整形(Noise Shaping)，並以偽偽差動架構(Pseudo-Pseudo-Differential)來解決單端系統的非線性問題，再採用一個六位元的逐次逼近之類比數位轉換器(SAR ADC)和比較器用來組成另一個多級雜訊整形架構，此架構有助於解決多位元數位類比轉換器(DAC)的非線性問題，同時提升有效位元(ENOB)。此電路在TSMC 180nm製程實現，晶片核心面積為0.466平方毫米，功耗為191.7微瓦，在1 kHz的頻寬下實現了14.13位元的解析度，並達到了92.04 dB的動態範圍。 晶片二同樣採用離散時間三角積分調變器的架構，核心設計為一個二階調變器，並結合一階雜訊耦合(Noise Coupling)整形技術，以實現三階雜訊整形。為了降低系統的功耗與面積，電路運用了運算放大器共享(OTA Sharing)技術，此外，量化器採用四位元的逐次逼近類比數位轉換器，以減少量化雜訊所帶來的干擾，同時以一增量加權平均演算法(Incremental Data Weight Average)來補償多位元數位類比轉換器因不匹配所產生的非線性諧波。此電路同樣在TSMC 180nm製程實現，晶片核心面積為0.273平方毫米，功耗為110.3微瓦，在16 kHz的頻寬下實現了14.5位元的解析度，並達到了170.7 dB的性能指標。 | zh_TW |
| dc.description.abstract | In modern Internet of Things (IoT) applications, a high-precision analog-to-digital converter (ADC) plays a crucial role in signal processing, directly impacting the overall system performance. This thesis proposes two different ADC architectures to meet the high-performance and low-power requirements of IoT devices.
Chip 1 is a discrete-time delta-sigma modulator (DTDSM) that employs a 2-1 multi-stage noise shaping to achieve high-order noise shaping. A six-bit successive approximation register (SAR) ADC and a comparator are used to form another multi-stage noise shaping structure, which helps to address the nonlinearity issues in multi-bit DAC and improve the resolution. Additionally, a pseudo-pseudo-differential architecture is adopted to mitigate nonlinearity issues in a single-ended system. This circuit is implemented in the TSMC 180nm process, with a core area of 0.466 mm² and a power consumption of 191.7 µW. It achieves a resolution of 14.13 bits within a 1 kHz bandwidth, a dynamic range of 92.04 dB. Chip 2 also adopts a DTDSM architecture, featuring a 2nd-order modulator combined with 1st-order noise coupling to achieve 3rd-order noise shaping. To reduce power consumption and chip area, the circuit employs the OTA sharing technique. Furthermore, a four-bit SAR ADC is used as the quantizer to minimize interference caused by quantization noise. An incremental data weight average algorithm is implemented to compensate for harmonic distortion caused by the mismatch in multi-bit DACs. It is also fabricated in the TSMC 180nm process, with a core area of 0.273 mm² and a power consumption of 110.3 µW. It achieves a resolution of 14.5 bits within a 16 kHz bandwidth, and a FoMSNDR of 170.7 dB. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-20T16:21:39Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-20T16:21:39Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 論文口試委員會審定書 ii
致謝 iv 摘要 vi Abstract viii Table of Contents x List of Figures xii List of Tables xvi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Fundamentals of Delta-Sigma Modulator ADC 4 2.1 Introduction and Building Block of DSM ADC 4 2.1.1 Loop Filter 5 2.1.2 Quantizer 6 2.1.3 DAC 8 2.2 Structure of DSM ADC 10 2.2.1 Cascade of Integrators with Distributed Feedback (CIFB) 10 2.2.2 Cascade of Integrators with Distributed Feedforward (CIFF) 11 2.2.3 Cascade of Resonators with Distributed Feedback (CRFB) 12 2.2.4 Cascade of Resonators with Distributed Feedforward (CRFF) 12 2.3 Noise Analysis of Switched-Capacitor Integrator 13 2.3.1 Noise Effect in Operational Amplifier 13 2.3.2 Noise Character in Switched-Capacitor Integrator 16 2.4 Summary 18 Chapter 3 Design of a Single-Ended Multi-Stage Noise Shaping 3rd-Order Discrete Time Delta-Sigma Modulator 20 3.1 Introduction 20 3.2 System Architecture 25 3.2.1 2-1 MASH 25 3.2.2 1-0 MASH 27 3.2.3 Pseudo-Pseudo-Differential 29 3.2.4 Conclusion 33 3.3 Circuit Implementation 34 3.3.1 Bootstrapped Switch 34 3.3.2 Rail-to-Rail Folded-Cascode Amplifier 35 3.3.3 VCM Based SAR ADC 37 3.3.4 Timing Generator 39 3.4 Measurement Results 41 3.4.1 Die Photo 41 3.4.2 Measurement Environment Setup 41 3.4.3 Measured Results 44 3.5 Summary 47 Chapter 4 Design of an OTA Sharing 2nd-Order Discrete Time Delta-Sigma Modulator with 1st-Order Noise-Coupling 49 4.1 Introduction 49 4.2 System Architecture 54 4.2.1 Noise-Coupling 55 4.2.2 OTA Sharing Architecture 56 4.2.3 Incremental Data Weight Averaging (IDWA) 57 4.3 Circuit Implementation 60 4.3.1 Current Reuse OTA 61 4.3.2 Noise-Coupling SAR 62 4.3.3 Timing Generator 64 4.4 Measurement Results 65 4.4.1 Die Photo 65 4.4.2 Measurement Environment Setup 66 4.4.3 Measured Results 68 4.5 Summary 71 Chapter 5 Conclusions and Future Works 72 5.1 Conclusions 72 5.2 Future Work 73 References 75 | - |
| dc.language.iso | en | - |
| dc.subject | 多級雜訊整形 | zh_TW |
| dc.subject | 雜訊整形 | zh_TW |
| dc.subject | 偽偽差動架構 | zh_TW |
| dc.subject | 雜訊耦合 | zh_TW |
| dc.subject | 運算放大器共享 | zh_TW |
| dc.subject | 增量加權平均演算法 | zh_TW |
| dc.subject | OTA sharing | en |
| dc.subject | Multi-Stage Noise Shaping | en |
| dc.subject | Noise Shaping | en |
| dc.subject | Noise Coupling | en |
| dc.subject | Incremental Data Weight Average | en |
| dc.subject | Pseudo-Pseudo-Differential | en |
| dc.title | 利用多級雜訊整形及雜訊耦合技巧之離散時間三角積分調變器設計 | zh_TW |
| dc.title | Design of Discrete-Time Delta-Sigma Modulators with MASH and Noise-Coupling Techniques | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;李泰成;鍾勇輝 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tai-Cheng Lee;Yung-Hui Chung | en |
| dc.subject.keyword | 多級雜訊整形,雜訊整形,偽偽差動架構,雜訊耦合,運算放大器共享,增量加權平均演算法, | zh_TW |
| dc.subject.keyword | Multi-Stage Noise Shaping,Noise Shaping,Pseudo-Pseudo-Differential,Noise Coupling,OTA sharing,Incremental Data Weight Average, | en |
| dc.relation.page | 79 | - |
| dc.identifier.doi | 10.6342/NTU202504416 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2025-08-15 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | N/A | - |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-113-2.pdf 未授權公開取用 | 4.45 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。