使用主動可變功率分配器實現Ka頻段雙輸出向量合成相移器

Abstract

本論文展示了一個應用於5G通訊系統之Ka頻段6位元雙輸出向量合成相移器(dual-output vector-sum phase shifter)，並採用台積電CMOS 180 nm製程實現。相較於傳統僅具單一輸出的相移器，所提出的雙輸出架構可同時輸出兩路訊號，不僅能讓相移器數量減半，功耗更是只要四分之一。雙輸出向量合成相移器的使用方式有兩種，一種是僅使用一個輸出的單輸出模式，與傳統相移器有相同的功能，另一種是同時使用到兩個輸出的雙輸出模式，兩種模式均具備6位元解析度。 電路架構包含主動可變功率分配器、雙相調變器及正交耦合器。主動可變功率分配器將輸入訊號分配為兩個不同振幅的訊號，雙相調變器可以反轉這兩個訊號的相位，最後使用正交耦合器合成兩個訊號，並同時輸出兩個訊號。 在中心頻率27.5 GHz下，單輸出模式的量測結果：S21振幅平均為0.97 dB，RMS振幅及相位誤差分別為0.21 dB及0.75°，S31振幅平均為1.28 dB，RMS振幅及相位誤差分別為0.12 dB及0.82°。在雙輸出模式下，S21及S31各自的振幅平均分別為1.9 dB及1.7 dB，雙輸出RMS振幅比誤差為0.91 dB，雙輸出RMS相位差誤差為0.3°。包含Pad的晶片佈局面積為0.89 mm2，而不含Pad的核心佈局面積則為0.54 mm2，整體直流功耗為9.6 mW。

This thesis presents a Ka-band 6-bit dual-output vector-sum phase shifter for 5G communication systems. The phase shifter is implemented in TSMC’s 0.18-µm CMOS technology. Compared to conventional single-output phase shifters, the proposed dual-output architecture simultaneously delivers two output signals, effectively reducing the number of required phase shifters by half and DC power consumption to one-fourth. The proposed dual-output phase shifter supports two modes of operation: a single-output mode, which functions equivalently to a traditional phase shifter, and a dual-output mode, which utilizes both outputs. Both modes have a resolution of 6 bits. The circuit architecture consists of an active variable power splitter, bi-phase modulator, and quadrature coupler. The active variable power splitter splits input signal into two signals with different amplitude, and the bi-phase modulator can inverse the phase of two signals, which will be synthesized by the quadrature coupler to produce two outputs at the same time. Measurement results at the center frequency of 27.5 GHz are as follows: in single-output mode, the average S21 gain is 0.97 dB, and S21 RMS gain and phase error are 0.21 dB and 0.75°, respectively. The average S31 gain is 1.28 dB, and S31 RMS gain and phase error are 0.12 dB and 0.82°, respectively. In dual-output mode, the average S21 and S31 gains are 1.9 dB and 1.7 dB, respectively. The dual-output RMS amplitude ratio error is 0.91 dB, and the dual-output RMS phase difference error is 0.3°. The chip size including the pads is 0.89 mm2 and the core size excluding the pads is 0.54 mm2. The measured DC power consumption is 9.6 mW.