請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98676完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | zh_TW |
| dc.contributor.advisor | Chung-Yang Huang | en |
| dc.contributor.author | 陳韋旭 | zh_TW |
| dc.contributor.author | Wei-Hsu Chen | en |
| dc.date.accessioned | 2025-08-18T01:18:51Z | - |
| dc.date.available | 2025-08-18 | - |
| dc.date.copyright | 2025-08-15 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-11 | - |
| dc.identifier.citation | A. Biere, A. Cimatti, E. Clarke, and Y. Zhu. Symbolic model checking without bdds. In W. R. Cleaveland, editor, Tools and Algorithms for the Construction and Analysis of Systems, pages 193–207, Berlin, Heidelberg, 1999. Springer Berlin Heidelberg.
A. R. Bradley. Sat-based model checking without unrolling. In R. Jhala and D. Schmidt, editors, Verification, Model Checking, and Abstract Interpretation, pages 70–87, Berlin, Heidelberg, 2011. Springer Berlin Heidelberg. R. Brayton and A. Mishchenko. Abc: An academic industrial-strength verification tool. In T. Touili, B. Cook, and P. Jackson, editors, Computer Aided Verification, pages 24–40, Berlin, Heidelberg, 2010. Springer Berlin Heidelberg. N. Een, A. Mishchenko, and R. Brayton. Efficient implementation of property directed reachability. In 2011 Formal Methods in Computer-Aided Design (FMCAD), pages 125–134, 2011. Hardware Model Checking Competition. HWMCC 2017 Benchmarks. https://hwmcc.github.io/, 2017. Accessed: 2025-07-18. J. Li, R. Dureja, G. Pu, K. Y. Rozier, and M. Y. Vardi. Simplecar: An efficient bug-finding tool based on approximate reachability. In H. Chockler and G. Weissenbacher, editors, Computer Aided Verification, pages 37–44, Cham, 2018. Springer International Publishing. K. L. McMillan. Interpolation and sat-based model checking. In W. A. Hunt and F. Somenzi, editors, Computer Aided Verification, pages 1–13, Berlin, Heidelberg, 2003. Springer Berlin Heidelberg. M. Sheeran, S. Singh, and G. Stålmarck. Checking safety properties using induction and a sat-solver. In W. A. Hunt and S. D. Johnson, editors, Formal Methods in Computer-Aided Design, pages 127–144, Berlin, Heidelberg, 2000. Springer Berlin Heidelberg. Y. Su, Q. Yang, Y. Ci, T. Bu, and Z. Huang. The ric3 hardware model checker, 2025. X. Zhang, S. Xiao, J. Li, G. Pu, and O. Strichman. Combining bmc and complementary approximate reachability to accelerate bug-finding. In 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 1–9, 2022. 楊承翰. 利用動態時間框架延展增進性質導向可達性技術. Master’s thesis, 國立臺灣大學, Jan 2017. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98676 | - |
| dc.description.abstract | 性質導向可達性(Property Directed Reachability, PDR)演算法為現今解決模型檢查(Model Checking)問題最有效之技術之一。然而,在一般典型的實現方法中,常因數量過多的回溯檢查(backtracking checks)而導致效率低落。雖然回溯檢查中大多數的證明義務(proof obligations)相對容易被阻擋,但少數困難的證明義務卻佔據了大比例的求解時間。為了解決此問題,我們提出一種多時間框架的性質導向可達性演算法,將動態時間框架擴展策略整合進多時間框架的轉移模型中,利用多時間框架電路之邏輯推論,以加速對困難證明義務之阻擋過程。
儘管這樣的整合在概念上看似簡單,先前的研究卻在正確性與完備性方面遭遇挑戰。本研究透過額外的精化機制克服這些問題,並提供形式化的正確性與完備性證明。 我們將所提出的演算法實作於兩個先進的性質導向可達性框架——ABC 與 rIC3——並以硬體模型驗證競賽(HWMCC)的基準測試集進行實驗評估。實驗結果顯示,與典型的單時間框架相比,我們的方法在效能上表現更為優異。 | zh_TW |
| dc.description.abstract | Property Directed Reachability (PDR) is one of the most effective techniques for solving model checking problems. However, in its typical implementation, it often suffers from excessive backtracking. While most proof obligations are relatively easy to block, a small number of difficult ones dominate the solving time. To address this inefficiency, we propose a multi-timeframe PDR algorithm that integrates a dynamic timeframe expansion strategy into a multi-timeframe transition framework. This design leverages reasoning across multiple timeframes to accelerate the blocking of difficult obligations.
Although this integration appears straightforward, prior attempts have encountered challenges regarding soundness and completeness. Our approach resolves these issues through additional refinement mechanisms, supported by formal proofs of correctness and completeness. We implement the proposed algorithm on two state-of-the-art PDR frameworks—ABC and rIC3—and evaluate it using benchmarks from the Hardware Model Checking Competition (HWMCC). Experimental results show that our approach consistently outperforms typical single-timeframe PDR in both frameworks. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-18T01:18:51Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-18T01:18:51Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Contents iv List of Figures vii List of Tables x Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Related Work on Multi-Timeframe PDR 2 1.3 Thesis Contributions 4 1.4 Thesis Organization 5 Chapter 2 Preliminary 6 2.1 Propositional Logic Foundations for Property Directed Reachability 6 2.2 Finite State Transition System 8 2.3 Model Checking 8 2.4 Property Directed Reachability Algorithm 9 Chapter 3 Motivation 14 3.1 Bottleneck Analysis of Typical Property Directed Reachability Implementations 15 3.2 Backtracking Depths in Difficult Proof Obligation Trees 16 3.3 Motivation for an Adaptive Multi-Timeframe Property Directed Reachability Algorithm 18 Chapter 4 The Challenges of Multi-Timeframe PDR 20 4.1 Notations and a Naïve Algorithm for Multi-Timeframe PDR 21 4.1.1 Notations 21 4.1.2 A Naïve Multi-Timeframe Property Directed Reachability Algorithm 22 4.2 Challenges on Correctness and Completeness 23 4.2.1 Valid Blocking When the Blocking Cube is an Original Proof Obligation 25 4.2.2 Invalid Blocking When the Blocking Cube is a Generalized Cube 26 4.3 Challenges on Efficiency 28 4.4 Summary 29 Chapter 5 The Proposed Multi-Timeframe Property Directed Reachability Algorithm 31 5.1 Overview of the Multi-Timeframe Property Directed Reachability Algorithm 32 5.1.1 Algorithm Description 32 5.1.2 Illustrative Example 38 5.2 CorrectnessandCompleteness 39 5.2.1 Invariant Property of Multi-Timeframe Property Directed Reachability 39 5.2.2 Proof of Correctness 43 5.2.3 Proof of Completeness 45 5.3 Dynamic Timeframe Expansion for Efficiency 46 Chapter 6 Case Study 47 6.1 UNSAFE Case:6s218b2950.aig 47 6.2 SAFE Case:6s310r.aig 49 Chapter 7 Experimental Results 52 7.1 Experimental Environment and Benchmarks 52 7.2 Results on HWMCC Benchmarks 53 7.3 Comparison with Pre-Expanded Timeframe Strategy 56 7.3.1 Overall Comparison 57 7.3.2 Pre-Expansion Before PDR vs. Dynamic Expansion During PDR 57 7.3.3 Multi-Timeframe PDR on Pre-Expanded Circuits 59 7.4 Effect of Multi-Timeframe PDR After Sequential Optimization 60 Chapter 8 Conclusions and Future Work 62 8.1 Conclusions 62 8.2 Future Work 63 References 64 | - |
| dc.language.iso | en | - |
| dc.subject | 模型檢查 | zh_TW |
| dc.subject | 正規驗證 | zh_TW |
| dc.subject | 時間框架延展 | zh_TW |
| dc.subject | 性質導向可達性技術 | zh_TW |
| dc.subject | 可滿足性問題 | zh_TW |
| dc.subject | Satisfiability Problem | en |
| dc.subject | Property Directed Reachability | en |
| dc.subject | Timeframe Expansion | en |
| dc.subject | Model Checking | en |
| dc.subject | Formal Verification | en |
| dc.title | 自適應多時間框架的性質導向可達性演算法 | zh_TW |
| dc.title | An Adaptive Multi-Timeframe Property Directed Reachability Algorithm | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 李念澤;王柏堯;Alan Mishchenko | zh_TW |
| dc.contributor.oralexamcommittee | Nian-Ze Lee;Bow-Yaw Wang;Alan Mishchenko | en |
| dc.subject.keyword | 正規驗證,模型檢查,可滿足性問題,性質導向可達性技術,時間框架延展, | zh_TW |
| dc.subject.keyword | Formal Verification,Model Checking,Satisfiability Problem,Property Directed Reachability,Timeframe Expansion, | en |
| dc.relation.page | 65 | - |
| dc.identifier.doi | 10.6342/NTU202503854 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2025-08-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電機工程學系 | - |
| dc.date.embargo-lift | 2025-08-18 | - |
| 顯示於系所單位: | 電機工程學系 | |
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