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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | zh_TW |
| dc.contributor.advisor | Chung-Yang Huang | en |
| dc.contributor.author | 郭亦翔 | zh_TW |
| dc.contributor.author | Y i-Hsiang Kuo | en |
| dc.date.accessioned | 2025-08-18T01:13:25Z | - |
| dc.date.available | 2025-08-18 | - |
| dc.date.copyright | 2025-08-15 | - |
| dc.date.issued | 2025 | - |
| dc.date.submitted | 2025-08-06 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/98651 | - |
| dc.description.abstract | 運算表(Tableau)是一種廣泛應用於量子電路最佳化技術的基礎表示方式,不僅支援相位合併策略,亦可應用於相位多項式最佳化方法,進一步降低小角度旋轉閘的使用量。然而,此類方法在合成階段常將運算表拆解為多個區段處理,導致額外的雙量子位元閘(如 CX)被引入,進而造成顯著的閘數開銷。 為了解決此問題,我們提出一種統一式的包立旋轉運算表合成技術,將分散的運算表區段整合為單一結構,並採用一種全域考量雙量子位元閘成本的合成方法,有效降低額外的 CX 閘使用。實驗結果顯示,相較於現有的技術,我們的方法在不同基準電路上分別可減少 45.93% 與 32.10% 的雙量子位元閘數量。 | zh_TW |
| dc.description.abstract | Tableau representations serve as a widely applicable foundation for various quantum circuit optimization (QCO) techniques, supporting not only phase-merging strategies but also phase-polynomial-like optimization methods that enable further T-count reduction. However, by decomposing the tableau into separate pieces, such methods often introduce redundant double-qubit gates—such as CXs—during synthesis, resulting in substantial CX-count overhead. To address this, we propose a unified Pauli-rotation synthesis technique that merges fragmented tableau pieces into a single structure and employs a CX-efficient holistic synthesis method. This approach significantly mitigates redundant CX gates during synthesis. Experimental results show that our method reduces CX count by 45.93% and 32.10% compared to state-of-the-art techniques across different benchmark sets. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2025-08-18T01:13:25Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2025-08-18T01:13:25Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements i
摘要 iii Abstract iv Contents v List of Figures viii List of Tables ix List of Algorithms x Denotations xi Chapter 1 Introduction 1 1.1 Quantum Circuit Optimization . . . . . . . . . . . . . . . . . . . . . 1 1.2 Tableau-based QCO . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Motivation and Problem Statement . . . . . . . . . . . . . . . . . . 3 1.4 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 2 Preliminaries 7 2.1 Basics of Quantum Circuits . . . . . . . . . . . . . . . . . . . . . . 7 2.2 From Quantum Circuit Synthesis to Optimization . . . . . . . . . . . 12 2.3 Tableau Representations . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Stabilizer States and Stabilizer Tableaux . . . . . . . . . . . . . . . 15 2.3.2 Pauli Rotations and Pauli Rotation Tableaux: . . . . . . . . . . . . 19 2.3.3 Diagonal Rotations and Phase Polynomials: . . . . . . . . . . . . . 22 Chapter 3 Problem Description 24 3.1 Tableau-Based QCO Flow . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 Convert Quantum Circuit to Tableau . . . . . . . . . . . . . . . . . 25 3.1.2 Phase Merging Optimization . . . . . . . . . . . . . . . . . . . . . 26 3.1.3 Phase-Polynomial-Like T-count Optimization . . . . . . . . . . . . 29 3.1.4 Tableau Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Limitations of Current Tableau Synthesis Method . . . . . . . . . . . 37 3.2.1 From Scattered Tableau Segments to Global Synthesis . . . . . . . 37 3.2.2 Barriers to Unified Tableau Synthesis . . . . . . . . . . . . . . . . 38 Chapter 4 Proposed Algorithm 41 4.1 Overview of the Proposed Method . . . . . . . . . . . . . . . . . . . 41 4.2 Detailed Description of the pMST Routine . . . . . . . . . . . . . . 43 4.2.1 Constructing the Dependency Graph . . . . . . . . . . . . . . . . . 44 4.2.2 Scheduling Target Rotations . . . . . . . . . . . . . . . . . . . . . 45 4.2.3 Synthesizing Rotations via a Global‐Cost MST Heuristic . . . . . . 46 4.3 Synthesizing the Residual Stabilizer Tableau . . . . . . . . . . . . . 52 Chapter 5 Experiment Results 56 5.1 Setup and Benchmark selection . . . . . . . . . . . . . . . . . . . . 56 5.2 Comparison within the Phase-Polynomial-Like Flow . . . . . . . . . 60 5.3 Comparison within the Phase-merging Optimization Flow . . . . . . 66 5.4 Comparison between Different QCO Schemes . . . . . . . . . . . . 70 Chapter 6 Contribution and Future Work 73 6.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 References 76 Appendix A — Clifford Propagation 81 | - |
| dc.language.iso | en | - |
| dc.subject | 量子計算 | zh_TW |
| dc.subject | 量子電路最佳化 | zh_TW |
| dc.subject | 穩定子運算表 | zh_TW |
| dc.subject | 包立旋轉運算表 | zh_TW |
| dc.subject | MST 啟發式演算法 | zh_TW |
| dc.subject | Stabilizer Tableau | en |
| dc.subject | Quantum Computing | en |
| dc.subject | Quantum Circuit Optimization | en |
| dc.subject | MST-based Heuristic | en |
| dc.subject | Pauli Rotation Tableau | en |
| dc.title | 以一體化包立旋轉合成法降低基於運算表之量子電路最佳化流程中之雙量子邏輯閘增量 | zh_TW |
| dc.title | Unified Pauli-Rotation Synthesis for Relieving CX-Count Overhead in Tableau-Based Quantum Circuit Optimization Flow | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江介宏;鄭皓中;洪士涵;邱大維 | zh_TW |
| dc.contributor.oralexamcommittee | Jie-Hong Jiang;Hao-Chung Cheng;Shih-Han Hung;Dah-Wei Chiou | en |
| dc.subject.keyword | 量子計算,量子電路最佳化,穩定子運算表,包立旋轉運算表,MST 啟發式演算法, | zh_TW |
| dc.subject.keyword | Quantum Computing,Quantum Circuit Optimization,Stabilizer Tableau,Pauli Rotation Tableau,MST-based Heuristic, | en |
| dc.relation.page | 82 | - |
| dc.identifier.doi | 10.6342/NTU202503794 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2025-08-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2030-08-04 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
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