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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9778完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 賴飛羆 | |
| dc.contributor.author | Hao Chen | en |
| dc.contributor.author | 陳豪 | zh_TW |
| dc.date.accessioned | 2021-05-20T20:40:47Z | - |
| dc.date.available | 2009-07-26 | |
| dc.date.available | 2021-05-20T20:40:47Z | - |
| dc.date.copyright | 2008-07-26 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-22 | |
| dc.identifier.citation | [1] A. Bellaouar and M. I. Elmasry, Low-Power Digital VLSI Design – Circuits and Systems. Kluwer Academic Publishers, Norwell, MA, 1995.
[2] A. R. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Kluwer Academic Publishers, Norwell, MA, 1995. [3] K. Pagiamtzis and A. Sheikholeslami. Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey. IEEE Journal of Solid-State Circuits, 41(3):712– 727, March 2006. [4] J.-C. Chang C.-S. Lin and B.-D. Liu. A low-power precomputation-based fully parallel content-addressable memory. IEEE J. Solid-State Circuits, 38(4):654 662, April 2003. [5] Shanq-Jang Ruan, Chi-Yu Wu, and Jui-Yuan Hsieh. Low Power Design of Precomputation-Based Content-Addressable Memory. IEEE Trans. VLSI Syst., vol. 16, no. 3, page 331–335, Mar. 2008. [6] H. Miyatake, M. Tanaka, and Y. Mori, A design for high-speed low-power CMOS fully parallel content-addressable memory macros. IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956-968, June 2001. [7] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, A novel low power CAM design. in Proc. IEEE ASIC/SOC Conf., Sept. 2001, pp. 198-202. [8] H. Choi, M. K. Yim, J. Y. Lee, B. W. Yun, and Y. T. Lee, Low-power 4-way associative cache for embedded SOC design. in Proc. IEEE 2000 ASIC/SOC Conf., Sept. 2000, pp. 231-235. [9] K. Pagiamtzis, and A. Sheikholeslami, Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 383-386, Sep. 2003. [10] A. Roth, D. Foss, R. McKenzie, and D. Perry, Advanced ternary CAM circuits on 0.13μm logic process technology. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 465-468, Oct. 2004. [11] A. Efthymiou, and J. D. Garside, A CAM with mixed serial-parallel comparison for use in low energy caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 325-329, Mar. 2004. [12] F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, Fully parallel 30-MHz, 2.5-Mb CAM. IEEE Journal of Solid-state Circuits, pp. 1690-1696, vol. 33, no. 11, Nov. 1998. [13] C. A. Zukowski and S.-Y. Wang. Use of selective precharge for lowpower contentaddressable memories. In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), volume 3, pages 1788 – 1791, 1997. [14] T. Sakata S. Hanzawa and K. Kajigaya. A dynamic CAM based on a one-hot-spot block code-for millions-entry lookup. In Symp. VLSI Circuits Dig. Tech. Papers, pages 382 –385, 2004. [15] I. Arsovski and A. Sheikholeslami. A current-saving match-line sensing scheme for content-addressable memories. In IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pages 304 – 305, 2003. [16] T. Homma E. Komoto and T. Nakamura. A high-speed and compactsize JPEG Huffmandecoder using CAM. In Symp. VLSI Circuits Dig. Tech. Papers, pages 37 – 38, 1993. [17] T. Chandler I. Arsovski and A. Sheikholeslami. A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme. IEEE J. Solid-State Circuits, 38(1):155 – 158, January 2003. [18] T. Kohonen. Content-Addressable Memory. Springer, New York, 2nd. ed. edition, 1987. [19] K. Ishibashi, K. Komiyaji, H. Toyoshima, M. Minami, N. Ohki, H. Ishida, T.Yamanaka, T. Nagano, and T. Nishida, A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid-State Circuits, vol. 30, pp.1189-1195, Nov. 1995. [20] I. Arsovski and A. Sheikholeslami, A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories. IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1958–1966, Nov. 2003. [21] Y. J. Chang, S. J. Ruan, and F. Lai, Design and analysis of low power cache using two-level filter scheme. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 568–580, Aug. 2003. [22] K. Pagiamtzis and A. Sheikholeslami, Using cache to reduce power in content-addressable memories (CAMs). in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2005, pp. 369–372 [23] K. H. Cheng, C. H.Wei, and S. Y. Jiang, Static divided word matching line for low-power content addressable memory design. in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 2, pp. 23–26. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9778 | - |
| dc.description.abstract | 內容可定址記憶體常見於需要高速搜尋比對的應用當中，如今最主要的商業應用就是網路路由器了。它平行比對的機制雖具有高速的特性，卻造成了相當高的功率消耗。
過去曾有兩種以預先計算為基礎的內容可定址記憶體，一種是以區塊互斥或來取得參數，而另一種是以數一來取得參數。兩種架構功率消耗的降低方面都有很好的表現。數一的方法雖然有對應於同一參數的資料數量分佈不均勻的問題，但它獨有的7個電晶體的儲存元不但省電還能節省晶片面積。反之，區塊互斥或的架構雖然解決了參數分佈不均勻的問題，卻無法使用7個電晶體的儲存元。 本論文提出了一個新的方法，透過一個額外的編碼器，結合了以上兩者的優點。我們使用 Synopsys 公司的 HSIPCE 搭配 0.18 μm 的製程檔進行模擬。 根據模擬結果，相較於區塊互斥或的方法，本論文提出的方法增加了12.5％的搜尋延遲，但減低了平均功率消耗達23.6％，並且降低了功率-延遲乘積達14％，而在面積的使用上並無增加。 | zh_TW |
| dc.description.abstract | Content-addressable memory is widely used in the application requiring high search speed. The primary commercial application of CAMs today is Internet routers. Although it has the high speed characteristic due to the parallel comparison, it results in quite high power consumption.
There have been two precomputation-based CAMs proposed previously. One is to extract parameters by means of counting the number of 1’s within input data. Another is to extract parameters by the so called Block XOR method. Both of the two architectures have excellent performance in reducing power consumption. Though the 1’s count method has a problem that the number of data related to a single parameter is not uniform distributed, its unique 7T CAM cells not only reduce power consumption but also save chip area. Whereas the Block XOR method solved the problem of data distribution, it can not apply the 7T CAM cells. In this thesis, we proposed a novel method. Through an extra input encoder, we combined the advantage of both architectures mentioned above. We further implemented and simulated the whole architecture by Synopsys Hspice using 0.18 μm technology. Simulation results show that comparing to the Block XOR method, our method has 12.5% longer latency, but the reduction of average power and power-delay product reached 23.6% and 14% respectively. As for the area cost, it remains almost equal. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-20T20:40:47Z (GMT). No. of bitstreams: 1 ntu-97-J95921005-1.pdf: 1516945 bytes, checksum: 7b46988b39fd757f9c8d81d3eda449e6 (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | Contents
Abstract Contents …………………………………………………I List of Figures …………………………………………IV List of Tables……………………………………………VI Chapter 1 Introduction 1 1.1 Low Power Requirement 1 1.2 Power Dissipation in CMOS VLSI Circuit 2 1.2.2 Short-circuit Power 3 1.2.3 Leakage Power 4 1.2.4 Static Power 5 1.3 Content-Addressable Memory 6 1.3.1 CAM Overview 6 1.3.2 CAM Applications 7 1.4 Thesis Organization 9 Chapter 2 CAM Basics and Related Works 10 2.1 CAM Cells 10 2.1.1 WRITE Operation of a CAM Cell 12 2.1.2. READ Operation of a CAM Cell 12 2.2 Search Mechanism 13 2.3 Matchlines 15 2.3.1 NOR Matchline 16 2.3.2 NAND Matchline 17 2.3.3 Comparison 18 2.4 CAM Relative Research 18 Chapter 3 Encoded PB-CAM 21 3.1 Preliminary Work on PB-CAM 21 3.1.1 1’s Count 22 3.1.2 Block XOR 27 3.2 Encoded PB-CAM 31 3.2.1 XOR Parameter Extractor 31 3.2.2 Matchline Selection 32 3.2.3 Encoding Scheme 34 3.2.4 An Example of Proposed Encoded PB-CAM Operation 35 3.3 Encoded PB-CAM Benefits and Constraints 37 3.3.1 Encoded PB-CAM Benefits 37 3.3.2 Encoded PB-CAM Constraints 38 Chapter 4 SPICE Implementation 39 4.1 Specifications 40 4.2 Encoded PB-CAM Implementation 40 4.2.1 Parameter Extractor 41 4.2.2 Valid Bit Column 41 4.2.3 Parameter Storage Block 42 4.2.4 Bitline Buffer Implementation 43 4.2.5 Data Storage Block 44 4.2.6 Matchline Buffer 44 4.2.7 Input Encoder 44 Chapter 5 Simulation Results 46 5.1 Power Consumption 46 5.2 Latency 48 5.3 Area 49 Chapter 6 Conclusion 50 Bibliography 52 | |
| dc.language.iso | en | |
| dc.title | 以預先計算為基礎並結合互斥或參數分離器及七個電晶體記憶細胞元的低功率內容可定址記憶體 | zh_TW |
| dc.title | A Low Power Precomputation-based Content-Addressable Memory Combining Block XOR Parameter Extractor with
7T CAM Cell | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡坤霖,李鴻璋,張延任,張孟洲 | |
| dc.subject.keyword | 低功率,內容可定址記憶體,預先計算,編碼, | zh_TW |
| dc.subject.keyword | Low power,Content-Addressable Memory,Precomputation,Encode, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2008-07-24 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| ntu-97-1.pdf | 1.48 MB | Adobe PDF | 檢視/開啟 |
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