RISC-V 向量擴展指令集在 LLVM 編譯器中的自定義指令實現與最佳化

Abstract

近年來，RISC-V 指令集架構因其開源、模組化與可擴展性的特色而備受矚目，各種針對特定應用領域的擴充應運而生，而在現今講求高效能的時代下，SIMD 指令是提升 CPU 效能重要的一環。本論文圍繞在 SIMD 指令與 RISC-V 指令集架構上，旨在探討 LLVM 編譯器專門優化 SIMD 指令之 Loop Vectorization Pass 在 RISC-V 向量擴充 (RISC-V Vector Extension) 的循環優化表現，研究過程中比較了 RISC-V 與 ARM 在成本模型上的差異，辨識出特定程式碼下 RISC-V 損失的向量化機會，並透過實作自定義向量反轉指令 (vrev) 替換了 RISC-V 現有的指令組合，進而改善了現有 LLVM 在 RISC-V 上的優化限制，提供了更多向量化機會。 本研究闡述了在 LLVM 中設計並整合 vrev 指令的過程，包括修改指令選擇與程式碼生成的階段，使 LLVM 能在 RISC-V 架構中有更多優化循環程式碼的機會。為了評估實作的正確性與效能影響，我們也因此修改 QEMU 模擬器來模擬這個指令，將 QEMU 作為實驗平台，執行 LLVM 編譯後包含 vrev 指令的程式碼，並與未使用該指令的版本進行比較。最後使用 SPEC CPU 2006 以及 SPEC CPU 2017 基準測試套件來評估效能，結果顯示，透過 LLVM 支援自訂的 vrev 指令，在一些測試標準中，有了 2% 至 3% 的效能提升，說明了該自訂義指令在 RISC-V 向量擴充中提升效能的潛力。

In recent years, the RISC-V Instruction Set Architecture (ISA) has gained significant attention due to its open-source nature, modularity, and extensibility, giving rise to various domain-specific extension instruction sets. In today's era of high-performance computing, SIMD instructions play a crucial role in enhancing CPU performance. This thesis focuses on SIMD instructions and the RISC-V architecture, specifically examining the Loop Vectorization Pass in the LLVM compiler, which is dedicated to optimizing SIMD instructions for the RISC-V Vector Extension (RVV). During our research, we compared the cost model between RISC-V and ARM, identified specific code patterns where RISC-V misses vectorization opportunities. To address this problem, we implemented a custom vector reverse instruction (vrev) to improve the existing instruction set of RISC-V. This enhancement improves current optimization limitations in LLVM for RISC-V, providing more vectorization opportunities. This research focus on the process of designing and integrating the vrev instruction within LLVM, including modifications to the instruction selection and code generation phases, enabling LLVM to better optimize loop code for the RISC-V architecture. To evaluate the correctness and performance impact of our implementation, we modified the QEMU simulator to support this instruction, using it as an experimental platform to execute LLVM-compiled code containing the vrev instruction, comparing it with the default versions. Finally, performance evaluation using the SPEC CPU 2006 and SPEC CPU 2017 benchmark suites showed that supporting the custom vrev instruction natively in LLVM yields performance improvements ranging from 2% to 3% in certain benchmarks, demonstrating the potential performance benefits of this custom instruction in the RISC-V Vector Extension.