基於功耗軌跡分析的旁通道洩漏自動檢測與抑制

Abstract

近年來，隨著嵌入式系統和物聯網設備的廣泛應用，其安全性面臨日益嚴峻的挑戰。旁通道攻擊 (Side-Channel Attack, SCA) 作為一種強大的物理攻擊手段，能夠利用加密設備在運行過程中產生的物理洩漏信息（如功耗、電磁輻射、時間延遲等）來推斷敏感數據，對系統安全構成嚴重威脅。 本研究提出一個在邏輯閘層級自動化執行旁通道洩漏檢測與選擇性抑制的整合式框架。該框架透過計算晶片電路在運算過程中的功耗因不同密鑰所造成的差異，以評估洩漏程度並找出對密鑰資訊敏感的邏輯閘。針對檢測出的洩漏邏輯閘，本研究設計一種具有功耗隱藏特性的複合暫存器，並選擇性地替換原始電路中洩漏嚴重的暫存器，從而在降低晶片額外成本的前提下實現有效的洩漏抑制。 實驗結果顯示，相較於對整個電路進行全面防禦，本研究提出的選擇性防禦策略能夠在僅增加少量的面積開銷的同時，有效降低AES和PRESENT加密演算法硬體實作的旁通道洩漏風險。

In recent years, with the widespread application of embedded systems and Internet of Things (IoT) devices, their security has faced increasingly severe challenges. Side-Channel Attacks (SCAs), as a potent physical attack method, can deduce sensitive data by exploiting physical leakage information (such as power consumption, electromagnetic radiation, timing delays, etc.) generated by cryptographic devices during operation, posing a serious threat to system security. This research proposes an integrated framework for automated gate-level side-channel leakage detection and selective mitigation. The framework evaluates the degree of leakage and identifies logic gates sensitive to key information by calculating the power consumption differences in the chip circuit caused by different secret keys during computation. To address the detected leaking logic gates, this study designs a composite register with power-hiding characteristics and selectively replaces high-leakage registers in the original circuit. This approach achieves effective leakage suppression while minimizing additional chip costs. The experimental results indicate that, compared to a comprehensive defense of the entire circuit, the selective defense strategy proposed in this study can effectively reduce the side-channel leakage risk in hardware implementations of AES and PRESENT encryption algorithms while incurring only a small area overhead.