增進電壓域與時域降壓轉換器效能之技術

Abstract

設計手持式裝置之降壓轉換器時，主要的兩個挑戰是暫態響應及輕載時的電源轉換效率。若暫態響應不佳，將會導致電壓不穩定，進而影響裝置的正常運作或降低其性能。因此，維持穩定的電壓調節對於確保電子產品的可靠運作至關重要。此外，在輕載時，轉換效率較低會增加能源消耗，使裝置需要更頻繁地充電，進而縮短電池壽命。因此，最佳化暫態響應與電源轉換效率對於整體性能和使用者體驗是不可忽視的。常見的解決方案是使用採用固定導通時間(Constant On-Time，COT)式的降壓轉換器(Buck Converter)，因為其天生具有較快的暫態響應和自適性的輕載效率技術。為了更進一步提升其性能，本論文針對這兩個挑戰提出了兩項技術。第一項是加速暫態響應之技術，當負載發生變動時，其技術可以減少回至穩態的時間並將輸出電壓驟降(Voltage Dips)最小化。第二項技術則是透過自我調整方法實現近逆向電流最佳化校準(Near-Optimal Reverse Current Calibration，NORCC)，此技術可用於減少逆向電流，以提升輕載之效率。本研究所提出的COT降壓轉換器使用台積電0.18-μm CMOS製程實現。量測結果顯示，當負載從100 mA變化至1.5 A時，最佳穩態時間為960 ns，電壓驟降最大減至50 mV。而電源轉換效率在10 mA至1.7 A之間皆大於79 %，在300 mA時，負載電流具有最高效率93.6 %。 此外，由於COT降壓轉換器的工作頻率與負載成正比，這種頻率變化可能對後端設備產生不利影響，並容易引發難以消除的電磁干擾(EMI)問題。此外，COT 轉換器通常表現出較差的負載調節性能，主要是因為它依賴輸出電壓的漣波進行控制，而這又會影響輸出電壓的準確性。儘管存在這些挑戰，COT 轉換器仍具有顯著優勢在於其快速的暫態響應，這使其在需要精確電壓調節的應用中具有一定的挑戰。因此，本論文提出了一種既能實現出色負載調節率，又能有效降低 EMI 干擾的解決方案。具體來說，採用了額外的電流前饋電路和第二型補償器(Type-II Compensator)，以消除對等效串聯電阻(RESR)的依賴，從而確保輸出電壓 (VOUT)的準確度。此外，提出透過無突波導通時間產生器(SFOTG)技術，以降低 EMI 對後端敏感電路的影響。本研究採用台積電 0.18-μm CMOS製程實現，晶片有效面積為 0.7 mm²。量測結果顯示，負載調節率可達到 1.8 mV/A。輸出噪音相較於傳統 COT 降壓轉換器改善了 20.73 dB，並且在負載電流300 mA時達到最佳電源轉換效率89.1%。 最後，本論文提出了一個具有PI補償器和無限相位移延遲線(Infinite Phase Shift Delay Line，IPSDL)的時域連續導通/不連續導通(CCM/DCM)電流模式降壓轉換器。首先，此轉換器利用兩條控制路徑來實現操作。其中，一條是電壓穩定路徑 (VRP)，用以確保輸出電壓的準確性；另一條則是電流前饋路徑(CFFP)，用來簡化補償器設計。本研究所提出的時域 PI 補償器是由壓控振盪器(VCO)與 IPSDL 以級聯方式實現的。借助 IPSDL使得降壓轉換器能夠在寬頻率範圍內運作，同時能改善暫態響應。該降壓轉換器採用了台積電 0.18-μm CMOS 製程，能夠提供 3.3V 的輸入電壓，其輸出電壓可調範圍從 0.35V 到 2.6V，並且支持 CCM 與 DCM 兩種工作模式。根據測試結果，負載調節率約為 5.26 mV/A。當輸出電流從 1A 變化到 50 mA 時，輸出電壓的穩態時間為 8.4 μs；而當負載電流從 50 mA 改變到 1A 時，穩態時間可縮短至3 μs。轉換效率方面，在輸入電壓為 1.8V的條件下，其最大峰值達到了95.7%。

Two key challenges in designing regulators for handheld devices are load transient response and light-load efficiency. Poor transient response can lead to unstable voltage, which may disrupt the device's operation and lower overall performance. Therefore, maintaining stable voltage regulation is essential for reliable device function. Additionally, low efficiency under light loads increases power consumption, which in turn requires more frequent charging and shortens battery life. Consequently, optimizing both transient response and power conversion efficiency is crucial for enhancing overall performance and improving user satisfaction. To address these challenges, one common solution is the Constant On-Time (COT) buck converter, known for its fast transient response and adaptive light-load efficiency. However, to further improve its performance, this study proposes two techniques. First, a transient-enhanced method is introduced to reduce the time required to return to steady state and to minimize voltage dips during load changes. Second, a self-adjusting approach called Near-Optimal Reverse Current Calibration (NORCC) is proposed to reduce reverse current, thereby improving efficiency at light loads. The proposed COT buck converter is implemented using TSMC's 0.18-μm CMOS process. Measurement results show that when the load changes from 100 mA to 1.5 A, the settling time is only 960 ns and the maximum voltage dip is reduced to 50 mV. Moreover, the converter maintains a power conversion efficiency above 79% for loads ranging from 10 mA to 1.7 A, with a peak efficiency of 93.6% at a 300 mA load. In addition, since the operating frequency of a COT buck converter increases with the load, any change in frequency can negatively affect downstream circuits by causing electromagnetic interference (EMI) that is difficult to eliminate. Moreover, COT converters often exhibit poor load regulation because they rely mainly on the output voltage ripple for control, which reduces the accuracy of the output voltage. However, despite these challenges, COT converters still offer the advantage of fast transient response, making them useful for applications that require precise voltage regulation. To address these issues, this paper proposes a solution that improves load regulation and effectively reduces EMI. Specifically, the design incorporates an additional current feed-forward circuit and a Type-II compensator to remove the dependency on the output capacitor’s equivalent series resistance (RESR), thereby ensuring a more accurate output voltage (VOUT). Furthermore, a Spur-Free On-Time Generator (SFOTG) technique is used to lessen the impact of EMI on sensitive downstream circuits. Moreover, this design is implemented using TSMC's 0.18-μm CMOS process, resulting in a chip with an effective area of 0.7 mm². Measurement results show that the load regulation reaches 1.8 mV/A, the output noise is reduced by 20.73 dB compared to traditional COT buck converters, and the peak power conversion efficiency is 89.1% at a 300 mA load current. Finally, this study presents a time-domain current-mode buck converter that operates in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The converter features a PI compensator and an Infinite Phase Shift Delay Line (IPSDL). First, the design uses two control paths. One path, called the Voltage Regulation Path (VRP), ensures the output voltage is accurate. The other path, known as the Current Feed-Forward Path (CFFP), simplifies the compensator design. Furthermore, the proposed time-domain PI compensator is built by cascading a Voltage-Controlled Oscillator (VCO) with an IPSDL. This design allows the buck converter to work over a wide range of frequencies and improves its transient response. In addition, the converter is fabricated using TSMC's 0.18-μm CMOS process. It accepts an input voltage of 3.3 V and provides an adjustable output voltage ranging from 0.35 V to 2.6 V, supporting both CCM and DCM modes. According to test results, the load regulation is approximately 5.26 mV/A. Moreover, when the output current changes from 1 A to 50 mA, the steady-state time is 8.4 μs; when the load current changes from 50 mA to 1 A, the steady-state time is reduced to 3 μs. Finally, under an input voltage of 1.8 V, the converter achieves a peak efficiency of 95.7%.