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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電信工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97087
完整後設資料紀錄
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dc.contributor.advisor王暉zh_TW
dc.contributor.advisorHuei Wangen
dc.contributor.author李宜恒zh_TW
dc.contributor.authorYi-Heng Leeen
dc.date.accessioned2025-02-26T16:23:22Z-
dc.date.available2025-02-27-
dc.date.copyright2025-02-26-
dc.date.issued2024-
dc.date.submitted2025-02-13-
dc.identifier.citation[1] "What is 5G?" https://www.i-pex.com/library/article/what-is-5g (accessed.
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[4] D. I. J. Carpenter, L. Testi, N. Whyborn, A. Wootten, and N. Evans, Subject: The ALMA Development Roadmap, 2018.
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[8] E. Ma, C.-C. Chiong, Y.-S. Wang, and H. Wang, "A 6-58 GHz Low Power Consumption Distributed Amplifier with Multi-drive Inter-stack Coupling in 90-nm CMOS Process," in 2024 49th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz), 2024: IEEE, pp. 1-2.
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[10] K.-C. Chang, B.-Z. Lu, Y. Wang, C.-C. Chiong, and H. Wang, "A 17.7-42.9-GHz low power low noise amplifier with 83% fractional bandwidth for radio astronomical receivers in 65-nm CMOS," in 2020 IEEE Asia-Pacific Microwave Conference (APMC), 2020: IEEE, pp. 507-509.
[11] P. Qin and Q. Xue, "Compact wideband LNA with gain and input matching bandwidth extensions by transformer," IEEE microwave and wireless components letters, vol. 27, no. 7, pp. 657-659, 2017.
[12] A. Ershadi, S. Palermo, and K. Entesari, "A 22.2-43 GHz gate-drain mutually induced feedback low noise amplifier in 28-nm CMOS," in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021: IEEE, pp. 27-30.
[13] Z. Deng, J. Zhou, H. J. Qian, and X. Luo, "A 22.9–38.2-GHz dual-path noise-canceling LNA with 2.65–4.62-dB NF in 28-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3348-3359, 2021.
[14] C. Feng, X. P. Yu, W. M. Lim, and K. S. Yeo, "A compact 2.1–39 GHz self-biased low-noise amplifier in 65 nm CMOS technology," IEEE Microwave and Wireless Components Letters, vol. 23, no. 12, pp. 662-664, 2013.
[15] H. Chen, H. Zhu, L. Wu, W. Che, and Q. Xue, "A wideband CMOS LNA using transformer-based input matching and pole-tuning technique," IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 7, pp. 3335-3347, 2021.
[16] C. Zhao et al., "A K-/Ka-band broadband low-noise amplifier based on the multiple resonant frequency technique," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 8, pp. 3202-3211, 2022.
[17] Y.-S. Lin and K.-S. Lan, "Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 1851-1855, 2022.
[18] H.-C. Yeh, C.-C. Chiong, S. Aloui, and H. Wang, "Analysis and design of millimeter-wave low-voltage CMOS cascode LNA with magnetic coupled technique," IEEE transactions on Microwave Theory and Techniques, vol. 60, no. 12, pp. 4066-4079, 2012.
[19] A. Jahanian and P. Heydari, "A CMOS distributed amplifier with distributed active input balun using GBW and linearity enhancing techniques," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 5, pp. 1331-1341, 2012.
[20] C.-M. Hsu, Y. Wang, and H. Wang, "A 14-91 GHz Distributed Amplifier in 65-nm CMOS," in 2020 IEEE Asia-Pacific Microwave Conference (APMC), 2020: IEEE, pp. 1009-1011.
[21] 鄭又華, "應用於相位陣列收發系統之 E 頻段相移器, 天文接收機之 Ka 頻段低雜訊放大器與分散式放大器之研究," 2024.
[22] W.-H. Lin, J.-H. Tsai, Y.-N. Jen, T.-W. Huang, and H. Wang, "A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process," in 2009 European Microwave Conference (EuMC), 2009: IEEE, pp. 393-396.
[23] 陳潁, "微波低功耗低雜訊放大器與毫米波多爾蒂功率放大器的設計," 2019.
[24] E. Kobal, T. Siriburanon, R. B. Staszewski, and A. Zhu, "A compact, low-power, low-NF, millimeter-wave cascode LNA with magnetic coupling feedback in 22-nm FD-SOI CMOS for 5G applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 4, pp. 1331-1335, 2022.
[25] B.-Z. Lu, Y. Wang, Y.-C. Wu, C.-C. Chiong, and H. Wang, "A submilliwatt K-band low-noise amplifier for next generation radio astronomical receivers in 65-nm CMOS process," IEEE Microwave and Wireless Components Letters, vol. 30, no. 7, pp. 669-672, 2020.
[26] J. Zhang, D. Zhao, and X. You, "A 20-GHz 1.9-mW LNA using g m-boost and current-reuse techniques in 65-nm CMOS for satellite communications," IEEE Journal of Solid-State Circuits, vol. 55, no. 10, pp. 2714-2723, 2020.
[27] K.-C. Chang, Y. Wang, and H. Wang, "Design of a 1.8-mW K-Band Low Noise Amplifier with 19.3-dB Gain and 3.3-dB Noise Figure in 90-nm CMOS," presented at the 2021 IEEE Asia-Pacific Microwave Conference (APMC), 2021.
[28] Y.-H. Cheng, C.-C. Chiong, Y.-S. Wang, and H. Wang, "A 1.4-mW Ka-band Low Noise Amplifier Using Self-Resonant Transformer Matching in 90-nm CMOS Process," in 2023 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2023: IEEE, pp. 14-16.
[29] C.-C. Chien, Y. Wang, Y.-S. Ng, T.-W. Huang, C.-C. Chiong, and H. Wang, "A D-Band Frequency Doubler with Gm-Boosting Technique in 28-nm CMOS," in 2023 18th European Microwave Integrated Circuits Conference (EuMIC), 2023: IEEE, pp. 201-204.
[30] C.-H. Lai, Y. Wang, C.-C. Chiong, and H. Wang, "An Active G-Band Frequency Doubler with High 3 rd and 4 th Harmonic Suppression in 90-nm CMOS Process," in 2024 49th International Conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz), 2024: IEEE, pp. 1-2.
[31] P.-H. Tsai, Y.-H. Lin, J.-L. Kuo, Z.-M. Tsai, and H. Wang, "Broadband balanced frequency doublers with fundamental rejection enhancement using a novel compensated Marchand balun," IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 5, pp. 1913-1923, 2013.
[32] T.-Y. Chiu, "超寬頻且低功耗的可變增益分散式放大器與毫米波放大器之研究," 臺灣大學電信工程學研究所學位論文, vol. 2021, pp. 1-164, 2021.
[33] C. Wang and C.-H. Li, "A G-Band Frequency Doubler in 40-nm Digital CMOS for THz Applications," in 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2021: IEEE, pp. 1-3.
[34] H.-C. Lin and G. M. Rebeiz, "A 135–160 GHz balanced frequency doubler in 45 nm CMOS with 3.5 dBm peak power," in 2014 IEEE MTT-S International Microwave Symposium (IMS2014), 2014: IEEE, pp. 1-4.
[35] B. Cetinoneri, Y. A. Atesal, A. Fung, and G. M. Rebeiz, "$ W $-band amplifiers with 6-dB noise figure and milliwatt-level 170–200-GHz doublers in 45-nm CMOS," IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, pp. 692-701, 2011.
[36] X. Wang, J. Wen, and L. Sun, "A D-band balanced frequency doubler with marchand balun structure," in 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2019: IEEE, pp. 1-3.
[37] Y.-H. Lee, C.-C. Chiong, Y.-S. Wang, and H. Wang, "An Over 100% Fractional Bandwidth Low Noise Amplifier with Gate-Drain Transformer-Feedback in 90-nm CMOS Process," in 2024 19th European Microwave Integrated Circuits Conference (EuMIC), 2024: IEEE, pp. 359-362.
[38] "Kepler focal plane assembly." https://www.nasa.gov/image-article/kepler-focal-plane-assembly/ (accessed NOV 19, 2008).
[39] Y.-H. Lin, S.-C. Hsiao, J.-H. Tsai, and T.-W. Huang, "A 0.7-mW V-band transformer-based positive-feedback receiver front-end in a 65-nm CMOS," IEEE Microwave and Wireless Components Letters, vol. 30, no. 6, pp. 613-616, 2020.
[40] B. Razavi and R. Behzad, RF microelectronics. Prentice hall New York, 2012.
[41] 黃煒智, "寬頻且低功耗之毫米波放大器之設計," 臺灣大學電信工程學研究所學位論文, vol. 2022, pp. 1-108, 2022.
[42] Y.-J. Hwang et al., "ALMA2030 Band-4+ 5 receiver front-end wideband sensitivity upgrade: first year initial development and future plan," in Millimeter, Submillimeter, and Far-Infrared Detectors and Instrumentation for Astronomy XII, 2024, vol. 13102: SPIE, pp. 248-259.
[43] 蔡秉翰, "補償式馬遜平衡不平衡轉換器之設計及毫米波二倍頻器之應用," 2012.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/97087-
dc.description.abstract本論文分為三個主要部分。第一部分介紹了使用90奈米金氧半場效電晶體製程之應用於通訊系統的超寬頻低雜訊放大器設計與量測結果,。第二部分描述了使用同樣製程的應用於天文接收器設計的低功耗Ka頻段極低功耗低雜訊放大器設計與量測結果。最後一部分應用於天文接收機的90奈米G頻段倍頻器之設計與結果。
第一部分著重於用於通訊系統的超寬頻低雜訊放大器的設計。為了擴展帶寬,每級採用了閘極-汲極變壓器回授技術。使用源極去耦來實現同時的雜訊和阻抗匹配,並採用多階匹配來實現更寬的輸入匹配和級間匹配。測試結果顯示該設計具有良好的性能,在13.3至40.3 GHz的4-dB帶寬內,達到15.6 dB的峰值增益,雜訊指數範圍為2.3至4.8 dB。該設計的直流功耗僅為11.7 mW。晶片總面積為0.43平方毫米。
第二部分展示了一款為天文接收器設計的低功耗Ka頻段低雜訊放大器。為了擴展帶寬,每級同樣採用了閘極-汲極變壓器回授技術,並通過源極去耦實現同時的雜訊和阻抗匹配,以及多階匹配來增強輸入和級間匹配。此外,採用電流復用技術來提升整體增益。測試結果顯示,所設計的低雜訊放大器在11.1 GHz的3-dB帶寬內實現了16.9 dB的小信號增益。在32 GHz下,其雜訊指數為3.8 dB,功耗僅為4.97 mW。整體晶片面積為0.49平方毫米。
最後一部分介紹了為天文接收器電路設計的G頻段倍頻器。該倍頻器架構採用了推推式結構,並使用馬遜平衡器以改善相位相反且幅度相同的信號。此外,採用了浮接體技術來增強高頻性能。測試結果顯示,所提出的倍頻器實現了-11.9 dB的轉換增益,3-dB帶寬達到40 GHz。晶片總面積為0.315平方毫米。
zh_TW
dc.description.abstractThis thesis consists of three main parts. The first part presents the design and measurement results of an ultra-wideband low noise amplifier fabricated by 90-nm CMOS process for communication system. The second part describes the design and measurement results of a low power Ka-band low-noise amplifier (LNA) fabricated by 90-nm CMOS process for astronomical receiver. The last chapter discusses the design and measurement of a G-band frequency doubler fabricated by 90-nm CMOS process for astronomical receiver.
The first part focuses on an ultra-wideband low-noise amplifier for communication system. To extend the bandwidth, the gate-drain transformer-feedback technique is employed at each stage. Source degeneration is utilized for simultaneous noise and impedance matching. Multi-order matching for wider input matching and inter-stage matching. Measurement results demonstrate competitive performance, with a peak gain of 15.6 dB and a noise figure ranging from 2.3 to 4.8 dB across a 4-dB bandwidth spanning from 13.3 to 40.3 GHz. The DC power consumption of the design is only 11.7 mW. The total area with pads is 0.43 mm2.
The second part presents an low power Ka-band low noise amplifier (LNA) designed for astronomical receivers. To extend the bandwidth, the gate-drain transformer-feedback technique is employed at each stage. Source degeneration is utilized for simultaneous noise and impedance matching. Multi-order matching for wider input matching and inter-stage matching. The current reused use to enhance the overall gain. The measurement results demonstrate that the proposed low noise amplifier achieves a small signal gain of 16.9 dB with 3- dB bandwidth of 11.1 GHz. Moreover, the LNA presents a noise figure of 3.8 dB at 32 GHz with a low power consumption of 4.97 mW. The total chip area is 0.49 mm2.
The last part presents introduces G-band frequency doubler designed for circuit in astronomical receiver. The frequency doubler architecture uses push-push structure using marchard balun to improve signals with opposite phases and the same amplitude and adding body-floating to enhance high frequency performance. The measurement results show that the proposed frequency doubler achieves a conversion gain of -11.9 dB with 3-dB bandwidth of 40 GHz. The total chip area is 0.315 mm2.
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dc.description.tableofcontents口試委員審定書 i
致謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xv
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.1.1 5G and Satellite Communication System [1, 2] 1
1.1.2 Next-generation Radio Astronomical Receiving System [3-5] 2
1.1.3 ALMA Bands 4 & 5 Combination 3
1.2 Literature Surveys 4
1.2.1 Ultra-wideband Low Noise Amplifier in CMOS Process 4
1.2.2 Low Power Ka-band Low Noise Amplifier in CMOS Process 6
1.2.3 G-band frequency doubler in CMOS Process 7
1.3 Contributions 9
1.3.1 Ku to Ka-band LNA in CMOS process 9
1.3.2 Ka-band LNA in CMOS Process 10
1.3.3 G-band Frequency Doubler in CMOS Process 10
1.4 Thesis Organization 11
Chapter 2 Design of An Over 100% Fractional Bandwidth Low Noise Amplifier with Gate-Drain Transformer-Feedback in 90-nm CMOS Process 12
2.1 Introduction 12
2.2 The Design of Wideband LNA 14
2.2.1 Biasing Selection and Device Size Selection 14
2.2.2 Gate-Drain Transformer Feedback Technique[11] 23
2.2.3 Multi-Order Matching 31
2.2.4 Circuit Architecture 35
2.2.5 Post-layout Simulation Results 36
2.3 Measurement Results 41
2.4 Summary 45
Chapter 3 Design of 4.97-mW Ka-Band Low Noise Amplifier in 90-nm CMOS Process 47
3.1 Introduction [3-5] 47
3.2 The Design of Wideband LNA 51
3.2.1 Biasing Selection and Device Size Selection 51
3.2.2 Current Reused Technique[41] 60
3.2.3 Circuit Architecture 66
3.2.4 Post-layout Simulation Results 67
3.3 Measurement Results 73
3.4 Summary 76
3.5 Discussion 78
Chapter 4 Design of a G-band Frequency Doubler with Body-Floating in 90-nm CMOS Process 82
4.1 Introduction[42] 82
4.2 The Design of G-Band Frequency Doubler 84
4.2.1 Biasing and Device Size Selection 84
4.2.2 Push-Push structure 89
4.2.3 Marchand Balun Design[43] 90
4.2.4 Body-Floating Technique[32] 93
4.2.5 Circuit Architecture 96
4.2.6 Post-layout Simulation Results 97
4.3 Measurement Results 101
4.4 Trouble Shooting and Discussions 105
4.5 Summary 110
Chapter 5 Conclusions 112
REFERENCES 114
-
dc.language.isoen-
dc.subject低雜訊放大器zh_TW
dc.subject衛星通訊zh_TW
dc.subject5G通訊zh_TW
dc.subject天文接收器zh_TW
dc.subjectG頻段zh_TW
dc.subjectKa頻段zh_TW
dc.subjectK頻段zh_TW
dc.subjectKu頻段zh_TW
dc.subject互補式金氧半導體zh_TW
dc.subject倍頻器zh_TW
dc.subject變壓器匹配網路zh_TW
dc.subjectCMOSen
dc.subjectK-banden
dc.subjectKa-banden
dc.subjectG-banden
dc.subjectastronomical receiveren
dc.subject5G communicationen
dc.subjectsatellite communicationsen
dc.subjectKu-banden
dc.subjecttransformeren
dc.subjectlow noise amplifieren
dc.subjectfrequency doubleren
dc.title閘汲極變壓器回授低雜訊放大器與應用於天文接收機之G頻段頻率二倍頻器之研究zh_TW
dc.titleResearch of Gate-Drain Transformer Feedback Low-Noise Amplifier and G-band Frequency Doubler for Astronomical Receiveren
dc.typeThesis-
dc.date.schoolyear113-1-
dc.description.degree碩士-
dc.contributor.oralexamcommittee黃天偉;林坤佑;章朝盛;王雲杉zh_TW
dc.contributor.oralexamcommitteeTian-Wei Huang ;Kun-You Lin ;Chau-Ching Chiong;Yunshan Wangen
dc.subject.keyword互補式金氧半導體,倍頻器,低雜訊放大器,變壓器匹配網路,Ku頻段,K頻段,Ka頻段,G頻段,天文接收器,5G通訊,衛星通訊,zh_TW
dc.subject.keywordCMOS,frequency doubler,low noise amplifier,transformer,Ku-band,K-band,Ka-band,G-band,astronomical receiver,5G communication,satellite communications,en
dc.relation.page117-
dc.identifier.doi10.6342/NTU202500595-
dc.rights.note同意授權(限校園內公開)-
dc.date.accepted2025-02-13-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電信工程學研究所-
dc.date.embargo-lift2025-02-27-
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