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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電信工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96485
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dc.contributor.advisor王暉zh_TW
dc.contributor.advisorHuei Wangen
dc.contributor.author賴致學zh_TW
dc.contributor.authorChih-Hsueh Laien
dc.date.accessioned2025-02-19T16:11:05Z-
dc.date.available2025-02-20-
dc.date.copyright2025-02-19-
dc.date.issued2025-
dc.date.submitted2025-01-22-
dc.identifier.citation[1] European Southern Observatory: https://www.eso.org/public/teles-instr/alma/
[2] Y. -M. Chen, Y. Wang, C. -C. Chiong and H. Wang, "A 21.5-50 GHz Low Noise Amplifier in 0.15-μm GaAs pHEMT Process for Radio Astronomical Receiver System," 2021 IEEE Asia-Pacific Microwave Conference (APMC), Brisbane, Australia, 2021, pp. 7-9
[3] Di Francesco et al., “The science cases for building a Band 1 receiver suite for ALMA,” arXiv:1310.1604v3 [astro-ph.IM], Oct. 2013.
[4] S. Hao, J. Fu, Y. Huang and Z. Hong, "A high linearity variable gain LNA for WCDMA receiver front-end," 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 2010, pp. 752-754
[5] W. -Z. Huang, M. -H. Li, Y. -S. Ng, Y. Wang and H. Wang, "A V-band Double-Transformer-Coupling and Current Steering VGLNA in 90-nm CMOS," 2022 17th European Microwave Integrated Circuits Conference (EuMIC), Milan, Italy, 2022, pp. 134-136.K. Chang, RF and Microwave Wireless Systems, New York: Wiley, 2000.
[6] Y. -T. Chang, Y. -N. Chen and H. -C. Lu, "A 38 GHz Low Power Variable Gain LNA Using PMOS Current-Steering Device and Gm-Boost Technique," 2018 Asia-Pacific Microwave Conference (APMC), Kyoto, Japan, 2018. pp. 654-656
[7] K. -C. Chang, Y. Wang and H. Wang, "A Broadband Variable Gain Low Noise Amplifier Covering 28/38 GHz bands with Low Phase Variation in 90-nm CMOS for 5G Communications," 2021 IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, USA, 2021.
[8] Y. Yi, D. Zhao and X. You, "A Ka-band CMOS Digital-Controlled Phase-Invariant Variable Gain Amplifier with 4-bit Tuning Range and 0.5-dB Resolution," 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018, pp. 152-155
[9] Ying Chen, "Design of microwave ultra-low-power low noise amplifer and millimeter-wave Doherty power amplifier,"National Taiwan University Master Thesis,2019
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[13] Y. Chai, Y. Liang, L. Li and T. Cui, "A 60-GHz CMOS Broadband LNA with Low-K Transformer-Based Matching Networks," 2018 International Conference on Microwave and Millimeter Wave Technology (ICMMT), Chengdu, China, 2018
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[17] M. Elkholy, S. Shakib, J. Dunworth, V. Aparin and K. Entesari, "A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 1, pp. 64-66, Jan. 2018.
[18] T. Wu, C. Zhao, H. Liu, Y. Wu, Y. Yu and K. Kang, "A 20 ~ 43 GHz VGA with 21.5 dB Gain Tuning Range and Low Phase Variation for 5G Communications in 65-nm CMOS," 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019, pp. 71-74
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[21] H. -S. Chen, H. -C. Chang, W. -C. Huang and J. Y. -C. Liu, "A W-band Frequency Doubler with Differential Outputs in 90-nm CMOS," 2019 IEEE Asia-Pacific Microwave Conference (APMC), Singapore, 2019
[22] P. -H. Tsai, Y. -H. Lin, J. -L. Kuo, Z. -M. Tsai and H. Wang, "Broadband Balanced Frequency Doublers With Fundamental Rejection Enhancement Using a Novel Compensated Marchand Balun," in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 5, pp. 1913-1923, May 2013
[23] X. Wang, J. Wen and L. Sun, "A D-band Balanced Frequency Doubler with Marchand Balun Structure," 2019 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Nanjing, China, 2019
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[25] B. Cetinoneri, Y. A. Atesal, A. Fung and G. M. Rebeiz, “W -Band Amplifiers With 6-dB Noise Figure and Milliwatt-Level 170–200-GHz Doublers in 45-nm CMOS,” in IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, pp. 692-701, March 2012
[26] B. -Y. Chen, Y. -H. Hsiao and H. Wang, "A broadband doubler with harmonic rejection in 90nm CMOS," 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Sendai, Japan, 2015
[27] S. Lee et al., "An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 170-172
[28] K. Takano, "A Doubler-based 300-GHz CMOS Up-Conversion Mixer for Terahertz Communication," 2019 12th Global Symposium on Millimeter Waves (GSMM), Sendai, Japan, 2019, pp. 26-28.
[29] K. Takano et al., "17.9 A 105Gb/s 300GHz CMOS transmitter," 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2017, pp. 308-309
[30] J. A. Jayamon, J. F. Buckwalter and P. M. Asbeck, "Multigate-Cell Stacked FET Design for Millimeter-Wave CMOS Power Amplifiers," in IEEE Journal of Solid-State Circuits, vol. 51, no. 9, pp. 2027-2039, Sept. 2016.
[31] A. Agah, J. A. Jayamon, P. M. Asbeck, L. E. Larson, and J. F. Buckwalter, “Multi-drive stacked-FET power amplifiers at 90 GHz in 45 nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1148–1157, May 2014.
[32] W.-C. Sun and C.-N. Kuo, “A 19.1% PAE, 22.4-dBm 53-GHz parallel power combining power amplifier with stacked-FET techniques in 90-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2019, pp. 327–330.
[33] H. Bameri and O. Momeni, "A 200-GHz Power Amplifier With a Wideband Balanced Slot Power Combiner and 9.4-dBm P sat in 65-nm CMOS: Embedded Power Amplification," in IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3318-3330, Nov. 2021.
[34] K. Sekine, T. Hagiwara, K. Takano, S. Hara, A. Kasamatsu and Y. Umeda, "A 270 GHz CMOS Doubler-Based Up-Conversion Mixer with Output Amplitude Imbalance Detection," 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Hualien, Taiwan, 2021.
[35] K. Takano, R. Dong, S. Lee, S. Amakawa, T. Yoshida and M. Fujishima, "A 239-315 GHz CMOS Frequency Doubler Designed by Using a Small-Signal Harmonic Model," 2018 13th European Microwave Integrated Circuits Conference (EuMIC), Madrid, Spain, 2018, pp. 109-112.
[36] Wei-Zhi Huang, "Design of the Broadband and Low-Power Millimeter-Wave Amplifiers," National Taiwan University Master Thesis, 2022.
[37] IEEE Standard for High Data Rate Wireless Multi-Media Networks— Amendment 2: 100 Gb/s Wireless Switched Point-to-Point Physical Layer, IEEE Standard 802.15.3d-2017, 2017.
[38] T. S. Rappaport et al., "Wireless Communications and Applications Above 100 GHz: Opportunities and Challenges for 6G and Beyond," in IEEE Access, vol. 7, pp. 78729-78757, 2019
[39] T. S. Rappaport, J. N. Murdock, and F. Gutierrez, Jr., ``State of the art in 60-GHz integrated circuits and systems for wireless communications,'' Proc. IEEE, vol. 99, no. 8, pp. 13901436, Aug. 2011.
[40] J. Ma, R. Shrestha, L. Moeller, and D. M. Mittleman, ``Invited article: Channel performance for indoor and outdoor terahertz wireless links,'' APL Photon., vol. 3, no. 5, Feb. 2018, Art. no. 051601.
[41] Y. Wang, T. -Y. Chiu, C. -C. Chien, W. -H. Tsai and H. Wang, "An E-Band High-Performance Variable Gain Low Noise Amplifier for Wireless Communications in 90-nm CMOS Process," in IEEE Microwave and Wireless Components Letters, vol. 32, no. 9, pp. 1095-1098, Sept. 2022.
[42] Y. -T. Chang and H. -C. Lu, "A V-Band Low-Power Digital Variable-Gain Low-Noise Amplifier Using Current-Reused Technique With Stable Matching and Maintained OP1dB," in IEEE Transactions on Microwave Theory and Techniques, vol. 67, no. 11, pp. 4404-4417.
[43] Y.-K. Hsieh, J.-L. Kuo, H. Wang, and L.-H. Lu, “A 60 GHz broadband low-noise amplifier with variable-gain control in 65 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 11, pp. 610–612, Nov. 2011.
[44] M. Möck, İ. K. Aksoyak and A. Ç. Ulusoy, "A High-Efficiency D-Band Frequency Doubler in 22-nm FDSOI CMOS," 2022 17th European Microwave Integrated Circuits Conference (EuMIC), Milan, Italy, 2022, pp. 272-275.
[45] S. Hao et al., "An 8.3% Efficiency 96–134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line," 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), Hiroshima, Japan, 2020, pp. 1-2.
[46] N. Oz and E. Cohen, "A compact 105–130 GHz push-push doubler, with 4dBm Psat and 18% efficiency in 28nm CMOS," 2015 10th European Microwave Integrated Circuits Conference (EuMIC), Paris, France, 2015, pp. 101-104.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96485-
dc.description.abstract在這本論文由以下三個部分組成,一個Q頻段具主動負載之可變增益低雜訊放大器和一個G頻段具高三、四次諧波抑制主動二倍頻器的設計與量測結果。
首先是預計作為Q頻段接收機之可變增益低雜訊放大器,使用的製程為90奈米金氧半場效電晶體,電路第一級使用源極退化電感已達到雜訊和增益的最佳匹配,第二及第三級作為增益控制使用n-type金氧半場效電晶體作為可變主動負載來達到增益控制並且在增益降低的同時減少電路的功耗,以達到接收機更高的功率效率。量測結果顯示此低雜訊可變增益低雜訊放大器具有19 GHz (29-48GHz) 並且在32 GHz的頻率下有最高增益19 dB以及最低雜訊5.3 dB,8-dB增益控制範圍,在最高和最低增益下的功耗分別為25.3及14.3 mW。
第二部分提出應用於阿塔卡瑪大型毫米波陣列第四及五頻段之二倍頻器,使用的製程為90奈米金氧半場效電晶體。使用馬遜平衡器產生180°相位差訊號,並透過將偏壓點選在Class-B,利用電晶體的最高二次轉導達到倍頻效果,雖然波導管本身可以抑制基頻的訊號,但由於天文接收機中混頻器寬頻特性,高次諧波項依然可能被降頻至混頻器的輸出,因此本電路透過柴比雪夫低通濾波器以抑制三、四次諧波項。在10 dBm輸入功率下,量測結果顯示在頻率182 GHz有最高輸出功率2.3 dBm以及-7.7 dB的轉換增益,電路的輸出3-dB頻寬為158-204 GHz,擁有25.4%比例頻寬。
第三部分提出應用於300 GHz 相位陣列收發器之平方混合器,使用的製程為65奈米金氧半場效電晶體。此平方混合器之架構和推推倍頻器相似,將偏壓點選在Class-B以達到最大的混頻效果,平方混合器通過平方中頻(IF)訊號和本地振盪(LO)訊號來生成射頻(RF)信號,中頻訊號和本地振盪訊號的頻率一樣。第一級採用堆疊放大器使電路在高頻中達到高輸出高增益的效果。但是因為訊號產生器的限制,量測並不完整,只能量到頻寬內的四個頻率點,其餘皆為模擬結果。在 -10 dBm輸入功率下,量測結果顯示在頻率272 GHz有最高輸出功率-2.6 dBm以及-12.6 dB的轉換增益,電路的輸出3-dB頻寬為266-282 GHz。
zh_TW
dc.description.abstractThis paper presents two main sections: the design and measurement results of a Q-band variable gain low noise amplifier (VGLNA) with current control and a G-band active frequency doubler with high 3rd and 4th harmonic suppression.
The first part presents a Q-band variable gain low noise amplifier (VGLNA) fabricated in 90-nm COMS process. Source degeneration is used to achieve the optimal noise and gain matching at the first stage. An NMOS current control device is used at the second and third stages to achieve gain control and reduce power consumption while the circuit's gain decreases, which could enhance the efficiency of the receiver. Measurement results reveal this VGLNA offers a 19 GHz (29-48 GHz) 3-dB bandwidth and a peak gain of 19 dB appears at 32 GHz, and the lowest noise figure is 5.3 dB. An 8-dB gain control range, 25.3 and 14.3 mW power consumption at high and low gain mode respectability.
The second part introduces a frequency doubler with high 3rd and 4th harmonic suppression for the ALMA band 5 fabricated in 90-nm CMOS process. Using Marchand balun to generate differential signal. The transistor is operated at class B for the highest Gm2. Although the output waveguide would block the signal from baseband, the higher harmonics may still down-convert significant RF power to the IF output because the wide bandwidth nature of mixer in radio astronomical receiver. This circuit suppresses 3rd and 4th harmonics by Chebyshev low pass filter. The measured peak conversion gain of the doubler is -7.7 dB and 2.3 dBm output power at 182 GHz with 10 dBm input power, the 3-dB bandwidth of the doubler is 158-204 GHz with 25.4% fractional bandwidth.
The third part presents a square mixer applied to a 300 GHz phase-array transceiver, utilizing a 65 nm CMOS process. The architecture of this square mixer is similar to that of a push-push doubler, with the bias point set at Class-B to achieve maximum mixing performance. The square mixer generates radio frequency (RF) signals by squaring the intermediate frequency (IF) signal and the local oscillator (LO) signal, which are at the same frequency. The first stage employs a stacked amplifier to achieve high output and gain at high frequencies. However, due to the limitations of the signal generator, the measurements are not complete, and only four frequency points within the bandwidth could be measured, with the rest being simulated results. At an input power of -10 dBm, the measurement results show the highest output power of -2.6 dBm and a conversion gain of -12.6 dB at a frequency of 272 GHz, with the circuit's output 3-dB bandwidth ranging from 266 to 282 GHz.
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dc.description.tableofcontents口試委員會審定書 i
致謝 i
中文摘要 iv
ABSTRACT v
CONTENTS vii
LIST OF FIGURES x
LIST OF TABLES xvii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.1.1 Astronomical Observation of the Universe 1
1.1.2 Bands 4 & 5 Combination 2
1.1.3 300-GHz Phase-Array Transceiver System 2
1.2 Literature Survey 3
1.2.1 Q-Band VGLNA in CMOS Process 3
1.2.2 G-band Doubler in CMOS Process 5
1.2.3 280 GHz Square Mixer in CMOS Process 6
1.3 Contributions 9
1.3.1 Q-Band VGLNA in CMOS process 9
1.3.2 G-band Frequency Doubler in CMOS Process 10
1.3.3 280 GHz Square Mixer in CMOS Process 10
1.4 Thesis Organization 11
Chapter 2 A 29-48 GHz Variable Gain Low Noise Amplifier Using Current Control in 90-nm CMOS Process 12
2.1 Radio Astronomy Receiver 12
2.2 The Design of Q-Band VGLNA 14
2.2.1 Device Size and Bias Selection 14
2.2.2 Source Degeneration Technique 19
2.2.3 Neutralization Capacitor Technique 22
2.2.4 Low-k Transformer Design 26
2.2.5 Current Control Design 28
2.3 Circuit Schematic and Post-Layout Simulation 33
2.4 Measurement Result 42
2.5 Summary 50
Chapter 3 An Active G-Band Frequency Doubler with High 3rd and 4th Harmonic Suppression in 90-nm CMOS Process 52
3.1 ALMA System Description 52
3.2 The Design of G-Band Frequency Doubler 54
3.2.1 Biasing and Device Size Selection 54
3.2.2 Marchand Balun Design. 60
3.2.3 Chebyshev Lowpass Filter Design 62
3.3 Simulation Result and Post-layout 64
3.4 Measurement Results 70
3.5 Summary 77
Chapter 4 A 266-282 GHz Square Mixer Design in 65-nm CMOS Process 78
4.1 Square Mixer 79
4.2 Design of 266-282 GHz Square Mixer 80
4.2.1 Biasing and Device Size Selection 80
4.2.2 Stacked Amplifier Design 84
4.2.3 Square Mixer Core Design 87
4.2.4 Marchand Balun Design 89
4.3 Circuit Schematic and Post-Layout Simulation 93
4.4 Measurement Result 100
4.5 Summary 109
Chapter 5 Conclusions 110
REFERENCE 112
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dc.language.isoen-
dc.subject寬頻放大器zh_TW
dc.subject300 GHzzh_TW
dc.subject平方混合器zh_TW
dc.subjectG頻段zh_TW
dc.subjectW頻段zh_TW
dc.subjectQ頻段zh_TW
dc.subject倍頻器zh_TW
dc.subject可變增益低雜訊放大器zh_TW
dc.subject低雜訊放大器zh_TW
dc.subject互補式金氧半導體zh_TW
dc.subjectvariable gain low noise amplifieren
dc.subjectQ banden
dc.subject300 GHzen
dc.subjectW banden
dc.subjectG banden
dc.subjectsquare mixeren
dc.subjectlow noise amplifieren
dc.subjectwideband amplifieren
dc.subjectCMOSen
dc.title應用於天文接收機之Q頻段可變增益低雜訊放大器、G頻段二倍頻器與相位陣列收發系統之平方混合器研究zh_TW
dc.titleResearch of Q-Band Variable Gain Low Noise Amplifier for Astronomy Receivers, G-Band Frequency Doubler, and Square Mixer for Phased Array Transceiver Systemsen
dc.typeThesis-
dc.date.schoolyear113-1-
dc.description.degree碩士-
dc.contributor.oralexamcommittee黃天偉;林坤佑;章朝盛;王雲杉zh_TW
dc.contributor.oralexamcommitteeTian-Wei Huang;Kun-You Lin;Chau-Ching Chiong;Yunshan Wangen
dc.subject.keyword互補式金氧半導體,寬頻放大器,低雜訊放大器,可變增益低雜訊放大器,倍頻器,Q頻段,W頻段,G頻段,平方混合器,300 GHz,zh_TW
dc.subject.keywordCMOS,wideband amplifier,low noise amplifier,variable gain low noise amplifier,Q band,300 GHz,W band,G band,square mixer,en
dc.relation.page119-
dc.identifier.doi10.6342/NTU202500223-
dc.rights.note同意授權(限校園內公開)-
dc.date.accepted2025-01-23-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電信工程學研究所-
dc.date.embargo-lift2025-02-20-
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