SHA3D 演算法基於FPGA 上硬體架構實作與分析

Abstract

本論文探討使用 SHA3D 作為挖礦演算法的虛擬貨幣 KCN 與 RedBlock，並在 FPGA 上進行硬體實作與加速優化。SHA3D 幣種是比特幣 (Bitcoin) 使用 POW (Proof of Work) 機制的延伸，但在處理交易打包、區塊生成和挖礦過程中，其哈希函數 (hash function) 使用的是 SHA3D，而非比特幣的 SHA-256。本研究專注於貨幣挖礦部分的硬體實作，當軟體獲取礦池區塊頭資料後，便將這些數據交由硬體進行重複哈希運算，直到找到符合難度條件的答案為止。

SHA3D 是一種計算密集型 (compute-hard) 算法，會大量使用 FPGA 板上的邏輯運算資源與暫存器。由於硬體資源有限，此類算法設計的目的是防止 ASIC 及 FPGA 等客製化硬體壟斷挖礦市場。過往的比較通常使用與本論文所使用的 TH53 FPGA 售價相近的 RTX 3070 GPU 作為基準進行 hash rate 的性能比較。然而，由於市面上已存在一個 TH53 FPGA 3.7Gh/s 的 bitstream，本論文會以此為基準進行性能優化。

TH53 FPGA 搭載 Xilinx Virtex Ultrascale+ VU33P 晶片，設計流程採用 Synopsys VCS 與 nWave 進行 RTL 撰寫，後端流程則使用 Xilinx Vivado 完成synthesis、place & route 以及 bitstream 的生成與燒錄，並在最終工作電壓調整使用 TUL (撼訊) 提供的電壓整 bitstream 進行微調，最終實現4.0Gh/s的hash rate，較現有市面上版本提升7.5%。論文詳細描述了架構修改與優化的過程，並在結尾對不同版本的數據進行了全面比較。

This thesis explores the hardware implementation and acceleration optimization of the cryptocurrencies KCN and RedBlock, which use the SHA3D algorithm for mining, on FPGA. SHA3D is an extension of the Proof of Work (PoW) mechanism used by Bitcoin, but instead of using Bitcoin's SHA-256 hash function during transaction packaging, block generation, and mining, SHA3D coins use the SHA3D hash function. This research focuses on the hardware implementation of cryptocurrency mining, where the block header data obtained from the mining pool by software is passed to the hardware for repetitive hashing operations until a solution that meets the difficulty target is found.

SHA3D is a compute-hard algorithm that extensively utilizes the logic resources and registers on the FPGA board. Since hardware resources are limited, such algorithms are designed to prevent the monopolization of mining by custom hardware such as ASICs and FPGAs. Previous comparisons typically used an RTX 3070 GPU, priced similarly to the TH53 FPGA used in this thesis, as a performance benchmark for hash rate. However, since there is already a 3.7 Gh/s bitstream available for the TH53 FPGA, this thesis uses that as a baseline for performance optimization.

The TH53 FPGA is equipped with a Xilinx Virtex Ultrascale+ VU33P chip. The design process involves using Synopsys VCS and nWave for RTL development, while the back-end process is handled using Xilinx Vivado for synthesis, place & route, and bitstream generation and programming. For final voltage adjustments, the voltage-regulated bitstream provided by TUL is used, ultimately achieving a hash rate of 4.0 Gh/s, which is a 7.5% improvement over the current available version. The thesis details the architecture modifications and optimizations made and concludes with a comprehensive comparison of different versions of the design data.