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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張子璿 | zh_TW |
| dc.contributor.advisor | Tzu-Hsuan Chang | en |
| dc.contributor.author | 莊函倫 | zh_TW |
| dc.contributor.author | Han-Lun Chuang | en |
| dc.date.accessioned | 2024-11-28T16:30:05Z | - |
| dc.date.available | 2024-11-29 | - |
| dc.date.copyright | 2024-11-28 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-10-07 | - |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96270 | - |
| dc.description.abstract | 近十年來，電晶體的發展遵循摩爾定律，該定律預測集成電路上電晶體密度大約每18 個月會翻倍。然而，傳統的電晶體微縮過程中遇到了物理和製程上的限制，使得難以按預測的速度繼續往前推進。為了維持摩爾定律的進展，科學家進一步地創新半導體技術。
最初，電晶體的微縮始於平面電晶體。隨著傳統微縮方法接近極限，短通道效應是其中最嚴重之問題。進而引入了鰭式電晶體(FinFET)。FinFET 具有鰭狀通道，通道周圍環繞三柵結構，有效地緩解短通道效應。 本論文研究了通過使用氦離子束微影技術（HIBL）將次奈米厚的Ga2O3 應變層與矽異質整合，以提升傳統 FinFET 的電性能。HIBL 在奈米級製程中的具有良好的精確度，改善傳統電子束微影的限制，並且Ga2O3 與矽的整合旨在增強FinFET 的電特性。 研究中詳細地描述利用 HIBL 製作FinFET。包括旋塗光阻，利用氦離子束曝光，並測試劑量，劑量是實驗的關鍵之一，以確定不同光阻之特性和圖案尺寸的最佳劑量，然後應用優化的參數以高精確度製作奈米級FinFET。 通過先進的HIBL 技術，與次奈米厚的Ga2O3 應變層與矽異質整合，顯著改善了傳統FinFET 的電性。包括更小的次臨界擺幅、降低汲極引發位能障下降效應、遷移率更高，提升電晶體開關特性。 | zh_TW |
| dc.description.abstract | In recent decades, transistor development has aligned with Moore's Law, which predicts the doubling of transistor density on integrated circuits approximately every 18 months. However, the traditional approach to miniaturizing transistors has encountered physical and fabrication constraints, making it difficult for advancements to continue at the predicted rate. To sustain the progress suggested by Moore's Law, researchers have increasingly focused on innovative semiconductor technologies.
Initially, transistor scaling began with planar MOSFETs. As traditional scaling approaches neared their limits, short-channel effects became problem. The FinFET architecture was introduced. FinFETs feature a fin-shaped channel with a tri-gate structure that wraps around the channel, providing excellent electrostatics and the control of the current flow. This thesis investigates the enhancement of conventional FinFETs' electrical performance through the hetero integration of sub-nanometer thick Ga2O3 strain layers with silicon using helium ion beam lithography (HIBL). HIBL is utilized due to its superior resolution and precision in nanoscale patterning, overcoming the limitations of traditional electron beam lithography. The integration of Ga2O3, a wide bandgap semiconductor, with Si aims to enhance the FinFETs' electrical characteristics. The study begins with the detailed process of fabricating FinFET structures using HIBL. The method involves spinning a resist on the sample, exposing it to a helium ion beam, and processing the patterns through etching or lift-off techniques. Dose testing is crucial in this process to determine the optimal ion energy per unit area for different resist and pattern dimensions. The optimized parameters are then applied to fabricate nanoscale FinFETs with high precision. FinFETs with Ga2O3 integration demonstrate significant improvements, including higher drain current levels, lower subthreshold swing, and reduced drain-induced barrier lowering (DIBL). These enhancements indicate better current conduction, higher mobility, and improved switching characteristics, attributed to the Ga2O3 layer. The hetero integration of sub-nanometer thick Ga2O3 strain layers with Si, facilitated by the advanced patterning capabilities of HIBL, significantly improves the electrical performance of conventional FinFETs. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-11-28T16:30:05Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-11-28T16:30:05Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員審定書 .............................................................................................................. ii
致謝 ................................................................................................................................. iii 摘要 ................................................................................................................................. iv Abstract ........................................................................................................................... v Contents ......................................................................................................................... vii List of Figures ................................................................................................................. x List of Tables .............................................................................................................. xviii Chapter 1 Introduction ............................................................................................... 1 1.1 Moore’s Law Scaling and Technology Evaluation ...................................... 1 1.1.1 Moore’s Law ................................................................................................ 2 1.1.2 Physical challenges ..................................................................................... 4 1.1.3 Challenges of Fabricating Transistors ...................................................... 5 1.2 From planar MOSFET to FinFET to GAA ............................................... 10 1.2.1 Planar MOSFET ....................................................................................... 10 1.2.2 FinFET ........................................................................................................ 11 1.2.3 Gate-all-around FET (GAAFET) ............................................................ 12 1.3 Toward 3D Electronics ................................................................................. 14 1.3.1 Recent Development of 3D electronics .................................................... 15 1.3.2 3D integration ........................................................................................... 15 1.3.3 3D packaging ............................................................................................. 16 1.3.4 Vertical stacking transistor architectures ............................................... 17 CHAPTER 2 CFET ................................................................................................... 19 2.1 Physical definition of CFET......................................................................... 19 2.2 Monolithic CFET and Sequential CFET .................................................... 20 2.2.1 Monolithic CFET ...................................................................................... 20 2.2.2 Sequential CFET ...................................................................................... 22 2.2.3 The challenge of current CFET process ................................................. 24 2.2.4 Sequential integration of CFET .............................................................. 25 2.3 Wafer bonding for sequential integration .................................................. 25 2.3.1 Overview of wafer bonding Technologies ............................................... 26 2.3.2 Principles and Process of Oxide wafer bonding..................................... 27 2.3.3 From wafer bonding to hybrid bonding ................................................. 28 2.3.4 Principles of Hybrid Bonding .................................................................. 29 2.3.5 Processes of Hybrid Bonding ................................................................... 30 2.3.6 Application of Hybrid bonding in 3D IC integration ............................ 31 CHAPTER 3 Advanced technology: helium ion beam lithography and wide bandgap semiconductor: Ga2O3 ................................................................................. 33 3.1 Helium Ion beam lithography ..................................................................... 33 3.1.1 Negative photoresist dose Test layout design and result ....................... 38 3.1.2 Positive photoresist dose Test layout design and result ......................... 44 3.2 Wide Bandgap Semiconductor: Gallium oxide ......................................... 46 CHAPTER 4 Process development of different scale transistor and application on circuit ............................................................................................................................. 50 4.1 Conventional FinFET fabrication setup ..................................................... 50 4.1.1 Layout for Conventional FinFET ........................................................... 51 4.1.2 Fabrication process of conventional microscale FinFET ...................... 52 4.1.3 DC analysis of conventional microscale FinFET ................................... 58 4.2 Self-alignment ion implantation FinFET fabrication setup ..................... 60 4.2.1 Mask layout for self-alignment ion implantation FinFET .................... 61 4.2.2 Fabrication process of self-alignment ion implantation microscale FinFET ................................................................................................................... 64 4.2.3 DC analysis of self-alignment ion implantation microscale FinFET ... 70 4.2.4 Fabrication process of self-alignment ion implantation nanoscale FinFET ................................................................................................................... 71 4.2.5 DC analysis of self-alignment ion implantation nanoscale FinFET ..... 76 4.3 Voltage transfer characteristics of CMOS Inverter .................................. 77 CHAPTER 5 Conclusion and future works ............................................................ 79 5.1 Modify the misalignment in Helium Ion Beam Lithography ................... 79 5.2 GAAFET ....................................................................................................... 80 5.3 Sequential CFET .......................................................................................... 81 Reference ....................................................................................................................... 82 | - |
| dc.language.iso | en | - |
| dc.subject | 氦離子束微影 | zh_TW |
| dc.subject | 異質整合 | zh_TW |
| dc.subject | 鰭式電晶體 | zh_TW |
| dc.subject | 次奈米厚 Ga2O3 應變層 | zh_TW |
| dc.subject | 寬能隙半導體 | zh_TW |
| dc.subject | Helium ion beam lithography | en |
| dc.subject | Sub-nanometer thick Ga2O3 strain layer | en |
| dc.subject | Wide Bandgap Semiconductor | en |
| dc.subject | FinFETs | en |
| dc.subject | Hetero integration | en |
| dc.title | 應用氦離子束微影技術製作奈米級電晶體並透過次奈米厚Ga2O3應變層與Si異質整合改善傳統FinFET的電性 | zh_TW |
| dc.title | Application of Helium Ion Beam Lithography and Electrical Performance Improvement of Conventional FinFETs through Hetero Integration of Sub-nanometer Thick Ga2O3 Strain Layer with Si | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 113-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 林致廷;陳敏璋;吳肇欣 | zh_TW |
| dc.contributor.oralexamcommittee | Chih-Ting Lin;Miin-Jang Chen;Chao-Hsin Wu | en |
| dc.subject.keyword | 氦離子束微影,寬能隙半導體,次奈米厚 Ga2O3 應變層,鰭式電晶體,異質整合, | zh_TW |
| dc.subject.keyword | Helium ion beam lithography,Wide Bandgap Semiconductor,Sub-nanometer thick Ga2O3 strain layer,FinFETs,Hetero integration, | en |
| dc.relation.page | 86 | - |
| dc.identifier.doi | 10.6342/NTU202404404 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-10-07 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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