具有聯合相位與頻率補償技術之快速鎖定鎖相迴路

Abstract

本論文提出了一種具有聯合相位與頻率補償技術的快速鎖定之鎖相迴路。在最大相位誤差偵測器的幫助下，頻率獲取過程完成後會立即補償累積的相位誤差與電壓差，以加速鎖相迴路的鎖定時間。

此鎖相迴路利用28奈米技術製造並以供應電壓0.9伏進行量測，在1.012百億赫茲的輸出頻率下，該鎖相迴路功耗為2.76毫瓦。而均方根抖動由一萬赫茲積分至一億赫茲為491飛秒。整體的穩定時間在穩定精準度為0.02百分率下提升了78百分率。

In this thesis, we propose a fast-locking phase-locked loop (PLL) with joint phase and frequency compensation technique. With the aid of a maximum phase error detector (MPED), the accumulated phase error is compensated immediately after completing the frequency acquisition process, thereby improving the settling time of the PLL.

A prototype chip operating at a supply voltage of 0.9 V was fabricated using a 28-nm CMOS process. The output frequency of the PLL is 10.12 GHz, with a power consumption of 2.76 mW. The integral root-mean-square jitter over a range of 10 kHz to 100 MHz is 491 fs. The total settling time is improved by 78% under a settling accuracy of 0.02%.