請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96142
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林宗賢 | zh_TW |
dc.contributor.advisor | Tsung-Hsien Lin | en |
dc.contributor.author | 方家熙 | zh_TW |
dc.contributor.author | Chia-Hsi Fang | en |
dc.date.accessioned | 2024-11-15T16:08:46Z | - |
dc.date.available | 2024-11-16 | - |
dc.date.copyright | 2024-11-15 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-10-20 | - |
dc.identifier.citation | [1] X. An, S. Pan, H. Jiang and K. A. A. Makinwa, "A 0.01 mm2 10MHz RC frequency reference with a 1-point on-chip-trimmed inaccuracy of ±0.28% from -45°C to 125°C in 0.18μm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2023, pp. 60-62.
[2] K.-S. Park et al., "A 1.4μW/MHz 100MHz RC oscillator with ± 1030ppm inaccuracy from -40°C to 85°C after accelerated aging for 500 hours at 125°C," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2023, pp. 62-64. [3] Ç. Gürleyük, S. Pan and K. A. A. Makinwa, "A 16 MHz CMOS RC frequency reference with ±90 ppm inaccuracy from −45 °C to 85 °C," IEEE J. Solid-State Circuits, vol. 57, no. 8, pp. 2429-2437, Aug. 2022. [4] J. Jung et al., "A single-crystal-oscillator-based clock-management IC with 18× start-up time reduction and 0.68ppm/ºC duty-cycled machine-learning-based RCO calibration," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2022, pp. 58-60. [5] C.-Y. Lin, Y.-W. Huang and T.-H. Lin, "A ± 20-ppm -50°C-105°C 1-μA 32.768-kHz clock generator with a system-HFXO-assisted background calibration," in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 1-3, Nov. 2021. [6] S. Yang et al., "A 339-nW 32.768-kHz DFLL-based reference clock generator with an embedded temperature sensor," in Proc. 21st Int. SoC Design Conf. (ISOCC), Aug. 2024. [7] Fundamentals of quartz oscillators, accessed on Aug. 2024 [Online]. Available: http://www.leapsecond.com/hpan/an200-2.pdf [8] H. Yamada, H. Ura and H. Fujiyama, "620 MHz AT-cut fundamental crystal resonator," Proc. IEEE Int. Freq. Control Symp. PDA Exhib., 2002, pp. 174-178. [9] C.-Y. Chang, C.-C. Yang and S.-S. Li, "A filter-free third overtone quartz oscillator based on micromachining technology," IEEE Trans. Ultrason., Ferroelectr., and Freq. Control, vol. 70, no. 6, pp. 577-584, June 2023. [10] H. Esmaeelzadeh and S. Pamarti, "A sub-nW 32-kHz crystal oscillator architecture based on a DC-only sustaining amplifier," IEEE J. Solid-State Circuits, vol. 54, no. 12, pp. 3247-3256, Dec. 2019. [11] H. J. Forster, "Thermal analysis of AT & SC-Cut quartz crystal resonators automated measurement method and results," in Proc. 36th Annual Freq. Cont. Symp., 1982, pp. 159-169. [12] P. C. Y. Lee and J. Wang, "Thickness-shear and flexural vibrations of contoured crystal strip resonators," in Proc. IEEE Ultrason. Symp., 1993, pp. 559-564. [13] L. M. Zhang et al., "Frequency-temperature relations of novel cuts of quartz crystals for thickness-shear resonators," in Proc. IEEE Int. Freq. Control Symp., 2018, pp. 1-4. [14] Cutting angles and frequency temperature characteristics, accessed on Aug. 2024 [Online]. Available: https://www.ndk.com/en/products/info/post_9.html [15] Statek TS series miniature quartz temperature sensor datasheet, accessed on Aug. 2024 [Online]. Available: https://statek.com/wp-content/uploads/2018/02/Temp-Sensor-10162-Rev-C.pdf [16] Crystal units: basic knowledge of how to measure the drive level, accessed on Aug. 2024 [Online]. Available: https://www.murata.com/enus/products/timingdevice/crystalu/overview/basic/drivelevel [17] Taitien XX type 3.2 x 2.5 mm SMD crystal datasheet, accessed on Aug. 2024 [Online]. Available: https://www.taitien.com/wp-content/uploads/2015/12/AT-0002_XX.pdf [18] C.-Y. Lin, Y.-W. Huang and T.-H. Lin, "A temperature-compensated crystal oscillator with piecewise polynomial varactor compensation achieving ±3.75-ppm inaccuracy from −30°C to 90°C," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 69, no. 4, pp. 2016-2020, April 2022. [19] S. Iguchi, H. Fuketa, T. Sakurai and M. Takamiya, "Variation-tolerant quick-startup CMOS crystal oscillator with chirp injection and negative resistance booster," IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 496-508. [20] M. Ding et al., "5.3 A 95μW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 90-91. [21] E. A. Vittoz, M. G. R. Degrauwe and S. Bitz, "High-performance crystal oscillator circuits: theory and application," IEEE J. Solid-State Circuits, vol. 23, no. 3, pp. 774-783, June 1988. [22] F. Bahmani and E. Sanchez-Sinencio, "A stable loss control feedback loop for VCO amplitude tuning," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2498-2506, Dec. 2006. [23] J. T. Santos and R. G. Meyer, "A one-pin crystal oscillator for VLSI circuits," IEEE J. Solid-State Circuits, vol. 19, no. 2, pp. 228-236, April 1984. [24] H. Esmaeelzadeh and S. Pamarti, "A quick startup technique for high-Q oscillators using precisely timed energy injection," IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 692-702, March 2018. [25] SiTime SiT9501 datasheet, accessed on Aug. 2024 [Online]. Available: https://www.sitime.com/support/resource-library/datasheets/sit9501-datasheet [26] R. Achenbach et al., "A digitally temperature-compensated crystal oscillator," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 1502-1506, Oct. 2000. [27] S. Farahvash, C. Quek and M. Mak, "A temperature-compensated digitally-controlled crystal Pierce oscillator for wireless applications," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 352-619. [28] Z. Wang et al., "An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 316-317. [29] Maxim/Analog Devices 10MHz to 51.84MHz TCXO datasheet, accessed on Aug. 2024 [Online]. Available: https://www.analog.com/media/en/technicaldocumentation/data-sheets/DS4026.pdf [30] Unlocking precision: exploring the advancements in TCXO technology, accessed on Aug. 2024 [Online]. Available: https://ecsxtal.com/store/pdf/Unlocking-Precision-Exploring-the-Advancements-in-TCXO-Technology.pdf [31] M.-D. Tsai et al., "A temperature-compensated low-noise digitally-controlled crystal oscillator for multi-standard applications," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), 2008, pp. 533-536. [32] Z.-Q. Zeng et al., "A high precision analog temperature compensated crystal oscillator using a new temperature compensated multiplier," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 70, no. 2, pp. 680-693, Feb. 2023. [33] S. Park et al., "A 43 nW, 32 kHz, ±4.2 ppm piecewise linear temperature-compensated crystal oscillator with ΔΣ-modulated load capacitance," IEEE J. Solid-State Circuits, vol. 57, no. 4, pp. 1175-1186. [34] K. Bult and H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation," IEEE J. Solid-State Circuits, vol. 22, no. 3, pp. 357-365, June 1987. [35] D. J. Comer and D. T. Comer, "Operation of analog MOS circuits in the weak or moderate inversion region," IEEE Trans. Education, vol. 47, no. 4, pp. 430-435, Nov. 2004. [36] A. S. Sedra and K. C. Smith, Microelectronic circuits. New York; Oxford University Press, 2015. [37] P. Malcovati, F. Maloberti, C. Fiocchi and M. Pruzzi, "Curvature-compensated BiCMOS bandgap with 1-V supply voltage," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1076-1081, July 2001. [38] J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen and H. E. Maes, "An easy-to-use mismatch model for the MOS transistor," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056-1064, Aug. 2002. [39] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and design of analog integrated circuits. New York; Wiley, 2017. [40] J. V. Faricelli, "Layout-dependent proximity effects in deep nanoscale CMOS," in Proc. IEEE Custom Integr. Circuits Conf., 2010, pp. 1-8. [41] K.-W. Su et al., "A scalable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics," in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 245-248. [42] R. J. Van De Plassche, "Dynamic element matching for high-accuracy monolithic D/A converters," IEEE J. Solid-State Circuits, vol. 11, no. 6, pp. 795-800, Dec. 1976. [43] P. Andreani and S. Mattisson, "On the use of MOS varactors in RF VCOs," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000. [44] R. L. Bunch and S. Raman, "Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs," IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1325-1332, Aug. 2003. [45] N. G. Toth et al., "23.7 A BJT-based temperature sensor with ± 0.1°C (3 σ ) inaccuracy from -55°C to 125°C and a 0.85pJ-K2 resolution FoM using continuoustime readout," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2023, pp. 358-360. [46] E. Sackinger and W. Guggenbuhl, "A versatile building block: the CMOS differential difference amplifier," IEEE J. Solid-State Circuits, vol. 22, no. 2, pp. 287-294, April 1987. [47] H. Banba et al., "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May 1999. [48] R. L. Brennan, T. R. Viswanathan and J. V. Hanson, "The CMOS negative impedance converter," IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1272-1275, Oct. 1988 [49] F. Fruett, G. Wang, and G. C. M. Meijer, “The piezojunction effect in NPN and PNP vertical transistors and its influence on silicon temperature sensors,” Sensors Actuators A, vol. 85, pp. 70–74, Sept. 2000. [50] R. Wang et al., "A Sub-1ppm/°C current-mode CMOS bandgap reference with piecewise curvature compensation," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 3, pp. 904-913, March 2018. [51] S. Iguchi, T. Sakurai and M. Takamiya, "A low-power CMOS crystal oscillator using a stacked-amplifier architecture," IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 3006-3017, Nov. 2017. [52] S.-H. Wen, K.-D. Chen, C.-H. Hsiao and Y.-C. Chen, "18.1 A -105dBc THD+N (-114dBc HD2) at 2.8VPP swing and 120dB DR audio decoder with sample-and-hold noise filtering and poly resistor linearization schemes," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2019, pp. 294-295. [53] S. N. Wooters, B. H. Calhoun and T. N. Blalock, "An energy-efficient subthreshold level converter in 130-nm CMOS," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 4, pp. 290-294, April 2010. [54] Y.-P. Chen, Y. Lee, J.-Y. Sim, M. Alioto, D. Blaauw and D. Sylvester, "45pW ESD clamp circuit for ultra-low power applications," in Proc. IEEE Custom Integr. Circuits Conf., 2013, pp. 1-4. [55] J. A. Kusters and J. R. Vig, "Thermal hysteresis in quartz resonators-a review (frequency standards)," in Proc. 36th Annual Freq. Cont. Symp., 1990, pp. 165-175. [56] Stress test qualification for passive components, accessed on Aug. 2024 [Online]. Available: http://www.aecouncil.com/Documents/AEC_Q200_Rev_D_Base_Document.pdf | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/96142 | - |
dc.description.abstract | 本論文提出一個基於差動對、全類比式的溫度補償技巧以改善溫度補償石英晶體振盪器之頻率隨溫度變化之穩定性。本作品中,我們使用三組差動對將溫度感測電路之輸出電壓進行三次多項式對應,再以對應後之電壓控制一組變容器,藉此補償石英晶體本身頻率隨溫度三次多項式變化之特性。本作提出之技巧被使用於一個以 90 奈米製程實作之 40 兆赫茲溫度補償石英晶體振盪器中。晶片面積為 0.455 平方毫米,於 -40~80°C 溫度範圍內達成 <±2.5 ppm 頻率變異,同時其溫度補償電路僅消耗整體 185 微瓦功耗之 16%。此作品之輸出在 10 千赫茲頻率偏移下量測得 -117.5 dBc/Hz 相位雜訊、4.5 皮秒之時脈抖動,表現上接近於其他溫度補償石英晶體振盪器作品。 | zh_TW |
dc.description.abstract | In this thesis, we present an all-analog, differential-pair-based technique to improve the frequency stability over temperature for temperature-compensated crystal oscillators (TCXO). By configuring three differential pairs to synthesize a cubic input-output characteristic, the proposed circuit maps the temperature sensor output to control a single varactor, compensating the cubic frequency error intrinsic to the crystal unit. Incorporating the proposed technique, a 40-MHz TCXO, which is fabricated in a TSMC 90-nm CMOS process, is demonstrated in this work. The TCXO occupies an active area of 0.455 mm2 and achieves a <±2.5 ppm frequency variation over the -40~80°C range, with its temperature-compensation blocks only consuming 16% of the overall 185-μW power. In terms of phase noise, the TCXO measures -117.5 dBc/Hz at 10 kHz offset with 4.5 psecrms integrated jitter, a level comparable to prior work. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-11-15T16:08:46Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-11-15T16:08:46Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 論文口試委員審定書 i
謝辭 v 摘要 vii Abstract ix List of Figures xv List of Tables xix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 2 Chapter 2 Fundamentals of Crystal Oscillators 3 2.1 Quartz Resonator 3 2.1.1 Physical Properties 3 2.1.2 Equivalent Electrical Model 4 2.1.3 Frequency and The Frequency-Pulling Effect 7 2.1.4 Temperature Dependence 8 2.1.5 Power Dissipation and Drive Level 9 2.1.6 Specifications of The Crystal Adopted in This Work 12 2.2 Crystal Oscillators (XO) 12 2.2.1 Three-Point-Oscillator Topology 12 2.2.2 Negative Resistance 13 2.2.3 Startup Time and Steady-State Amplitude 15 2.2.4 Pierce XO 16 Chapter 3 Temperature Compensation in Crystal Oscillators 19 3.1 Frequency-Pulling for Temperature Compensation 19 3.2 Implementations of Temperature Compensation 21 3.2.1 Digital Compensation 21 3.2.2 Analog Compensation 22 3.2.3 Piecewise-Linear Compensation 22 3.3 Summary 24 Chapter 4 Proposed Analog TCXO 26 4.1 Polynomial Generation Using Differential Pairs 26 4.1.1 Basic Concept 26 4.1.2 Quantitative Analyses 30 4.1.3 Practical Issues 35 4.1.4 Comparison with Prior Analog TCXOs 41 4.2 Full TCXO Architecture 42 4.3 Circuit Implementation 42 4.3.1 Available Baseband MOS in The Selected Process 42 4.3.2 Varactor and Capacitor Bank 44 4.3.3 XO Core 47 4.3.4 Positive-Temperature-Coefficient Voltage Generator 48 4.3.5 Polynomial Synthesizer 52 4.3.6 Bandgap Reference 56 4.3.7 Noise Filter 59 4.3.8 Voltage Reference Generator 62 4.3.9 SPI Interface 64 4.3.10 Pad and ESD Protection 65 4.4 Calibration 67 4.4.1 XO Tuning Gain 67 4.4.2 Temperature Compensation 68 Chapter 5 Measurement Results 70 5.1 Die Micrograph 70 5.2 Measurement Setup 70 5.2.1 Wire-bonding and Crystal Placement 70 5.2.2 Off-chip Peripherals and Instrument 71 5.3 Measurement Results 72 5.3.1 XO Tuning Curve 72 5.3.2 XO and TCXO Frequency Variations to Temperature 74 5.3.3 Phase Noise and Output Spectrum 75 5.3.4 Power Breakdown 76 5.4 Performance Summary 77 Chapter 6 Conclusions and Future Works 79 6.1 Conclusions 79 6.2 Future Works 79 References 83 | - |
dc.language.iso | en | - |
dc.title | 一個使用差動對多項式補償技巧之類比式溫度補償晶體振盪器 | zh_TW |
dc.title | An Analog TCXO With A Differential-Pair-Based Polynomial Temperature Compensation Technique | en |
dc.type | Thesis | - |
dc.date.schoolyear | 113-1 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 陳冠達;曾英哲 | zh_TW |
dc.contributor.oralexamcommittee | Kuan-Dar Chen;Ying-Che Tseng | en |
dc.subject.keyword | 石英晶體振盪器,溫度補償,溫度補償石英晶體振盪器,類比式溫度補償石英晶體振盪器,變容器, | zh_TW |
dc.subject.keyword | crystal oscillator (XO),temperature-compensation,temperature-compensated crystal oscillator (TCXO),analog TCXO,varactor, | en |
dc.relation.page | 90 | - |
dc.identifier.doi | 10.6342/NTU202404486 | - |
dc.rights.note | 未授權 | - |
dc.date.accepted | 2024-10-21 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-113-1.pdf 目前未授權公開取用 | 24.51 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。