一個具有展頻功能和有限衝激響應嵌入式雜訊過濾技術的 2.5GHz ∆Σ 非整數型鎖相迴路

Abstract

此篇論文以 ∆Σ 非整數型鎖相迴路為設計基礎，採用 T55 技術製造，並通過頻譜分析儀和商用 USB3.2 CTS 測試進行了測量。通過嵌入式 FIR 噪音過濾技術，打破了震盪器噪音和 ∆Σ 量化噪音之間的折衷。在相位噪音輪廓中，中頻段頻率大約有 10dB 的改善。提出了一種數位控制延遲器偏置生成和校準技術，以應對電荷泵線性問題。數位控制延遲器校準技術減少了 20% 的相位噪音。這種技術可以消除低頻率因電流泵線性度不佳造成的相位噪聲。採用取樣迴路濾波器技術以避免大的參考擾動。達到了-62.48dBc 的參考擾動的結果。最後，實現了 4500ppm的展頻功能以符合 USB3.2 CTS 測試。此設計在所有測項上都通過了 USB3.2 的商用規格。

A Delta-Sigma fractional-N PLL design isdemonstrated, fabrcated in T55 technol ogy and measured by spectrum analyzer and commercial USB3.2 CTS test. A trade-off between VCO noise and Delta-Sigma quantization noise is broken by embedded FIR noisefiltering technique. Around 10dB improves in mid band frequency could be found in phasenoise profile. A DCDL offset generation and calibration technique is proposed to deal with the charge pump linearity issue. 20% phase noise is reduced by DCDL calibration technique. The aliased low frequency is cancelled by such technique. Sampling Loop filter technique is used to avoid large reference spur. A -62.48dBc reference spur result is available. Finally, 4500ppm Spread spectrum function is implemented for the USB3.2 CTS test. All the specification are pass in such test with our design.