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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 洪士灝(Shih-Hao Hung) | |
dc.contributor.author | Chinag-Ruei Chen | en |
dc.contributor.author | 陳江睿 | zh_TW |
dc.date.accessioned | 2021-05-20T20:27:04Z | - |
dc.date.available | 2010-09-02 | |
dc.date.available | 2021-05-20T20:27:04Z | - |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-20 | |
dc.identifier.citation | [1] Kunle, O., Basem, A.N., Lance, H., Ken, W., and Kunyung, C., 'The Case for a Single-Chip Multiprocessor', Proc. 7th International Symposium on Architectural Supportfor Programming Languages and Operating Systems, vol. 31, no. 9, 1996.
[2] Jose, R., Karin, S., Luis, C., Wei, L., Smruti, S., James, T., and Josep, T., 'Thread-Level Speculation on a Cmp Can Be Energy Efficient', in Proceedings of the 19th annual international conference on Supercomputing, 2005 [3] Sungjoo, Y., Iuliana, B., Aimen, B., Yanick, P., and Ahmed, A.J., 'Building Fast and Accurate Sw Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer', in Proceedings of the conference on Design, Automation and Test in Europe - Volume 1, 2003 [4] In-Cheol, P., Sehyeon, K., and Yongseok, Y., 'Fast Cycle-Accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation', in Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, 2003 [5] A.Snavely, L.Carrington, and Wolter, N., 'Modeling Application Performance by Convolving Machine Signatures with Application Profiles', Proc. IEEE Workshop on Workload Characterization, 2001. [6] M.Mahoney, and T.Elrad, 'Modeling Platform Specific Attributes of a System as Crosscutting Concerns Using Aspect-Oriented Statecharts and Virtual Finite State Machines', the 6th International Workshop on Aspect-Oriented Modeling as part of AOSD05 Chicago,USA, 2005. [7] 'Simplescalar' http://www.simplescalar.com/ [8] 'Rsim' http://rsim.cs.uiuc.edu/rsim/dist.html [9] Magnusson, P.S., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., and Werner, B., 'Simics: A Full System Simulation Platform', Computer, vol. 35, no. 2, 2002. [10] 'SystemC' http://www.systemc.org/home [11] Chang, H.W., A Rapid Simulation Environment for Application Performance Estimation on Parameterized Multi-Core/Multi-Threading Architecture Models(2007) [12] Enrico, M., Massoud, P., and Fabio, S., 'High-Level Power Modeling, Estimation, and Optimization', in Proceedings of the 34th annual conference on Design automation, 1997 [13] Paul, L., 'High-Level Power Estimation', in Proceedings of the 1996 international symposium on Low power electronics and design, 1996 [14] Tony, D.G., Frank, V., J, and rg, H., 'Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripheral Cores', in Proceedings of the 13th international symposium on System synthesis, 2000 [15] C. Talarico, J. W. Rozenblit, V. Malhotra, and Stritter, A., 'A New Framework for Power Estimation of Embedded Systems', Computer, vol. 38, no. 2, 2005. [16] David, B., Vivek, T., and Margaret, M., 'Wattch: A Framework for Architectural-Level Power Analysis and Optimizations', in Proceedings of the 27th annual international symposium on Computer architecture, 2000 [17] Ye, W., Vijaykrishnan, N., Kandemir, M., and Irwin, M.J., 'The Design and Use of Simplepower: A Cycle-Accurate Energy Estimation Tool', in Proceedings of the 37th conference on Design automation, 2000 [18] 'Sim-Panalyzer Project' http://www.eecs.umich.edu/~panalyzer/ [19] Tan, T.K., Raghunathan, A.K., Lakishminarayana, G., and Jha, N.K., 'High-Level Software Energy Macro-Modeling', in Proceedings of the 38th conference on Design automation, 2001 [20] Tan, T.K., Raghunathan, A., and Jha, N.K., 'Energy Macromodeling of Embedded Operating Systems', Trans. on Embedded Computing Sys., vol. 4, no. 1, 2005. [21] Jinwen, X., Zhaohui, H., and Peixin, Z., 'Energy Macro-Modeling of Embedded Microprocessor Using Systemc', in Electro Information Technology, 2005 IEEE International Conference on, 2005, pp. 6 pp. [22] 'Intel Vtune Performance Analyzer' http://www.intel.com/software/products/vtune. [23] 'Sun Dtrace' http://www.sun.com/bigadmin/content/dtrace/ [24] 'GNU gprof' http://www.cs.utah.edu/dept/old/texinfo/as/gprof_toc.html [25] 'Valgrind' http://valgrind.org/ [26] 'ARM SoC Designer' http://www.arm.com/products/DevTools/RealViewSystemDevelopment.html [27] 'Mibench' http://www.eecs.umich.edu/mibench/ [28] Kiran, P., Kyu-Won, C., Jun Cheol, P., Vincent J. Mooney, III, Abhijit, C., and Peeter, E., 'System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory', in Proceedings of the 15th international symposium on System Synthesis, 2002 [29] David, W., Brinda, G., Nuengwong, T., Kathleen, B., Aamer, J., and Bruce, J., 'Dramsim: A Memory System Simulator', SIGARCH Comput. Archit. News, vol. 33, no. 4, 2005. [30] 'Micron Technology, Inc' http://www.micron.com/ [31] Gang, Q., Naoyuki, K., Kimiyoshi, U., and Miodrag, P., 'Function-Level Power Estimation Methodology for Microprocessors', in Proceedings of the 37th conference on Design automation, 2000 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9529 | - |
dc.description.abstract | 由於消費性電子產品的高度需求帶動了嵌入式系統的蓬勃發展,在快速導入市場的壓力之下,系統設計者在早期開發階段對於系統效能評估以及預測顯得特別重要。另外在這些電子產品中,可攜式裝置佔了大部分,系統功率消耗也成為了設計時期必須納入考量的因素。因此在本論文中,要探討的主題即為系統層級的效能及功率評估方法,透過評測分析應用程式的行為建立而成的應用程式模型及功率模型,放入根據目標平台參數所建立的硬體結構平台,進行交互模擬,提供一個快速的評估環境。我們使用Mibench作為目標應用程式,在效能部分,使用Cycle-Accurate 的ARM SoC Designer Simulator當作比較對象;功率部份,我們著重在記憶體系統的功耗,並且使用DRAMsim進行驗證。從實驗結果得知,模擬速度平均約有15倍至25倍的加速,效能評估誤差率在15%以下,功率評估誤差則在6%以下。從結果來看模擬的速度有顯著的提升,未來將致力於更精準的應用程式及硬體結構模型建構,以及加入其他功率消耗元件。 | zh_TW |
dc.description.abstract | Due to the high demand of the consumer electronics, embedded systems generally have short product design cycles. To shorten the time to market, system designers need a way to quickly validate the performance for the entire system in the early design stage. For battery-powered devices, power consumption is also critical issue.
Thus, we propose a simulation framework to estimate the performance and power consumption of memory system jointly using behavioral models. Our results showed that our simulation scheme reduced simulation time by up to 25X , compared to the ARM SoC Designer, a cycle-accurate simulator, while the error was controlled under 0.67%, 8.16% and 11.78% for single-core, dual-core and 4-core systems respectively. For the power consumption of the memory system, the error was under 6%. Thus, our framework provides a significant improvement of simulation speed over the traditional method and still delivers reasonable accuracy for joint performance and power consumption evaluation. | en |
dc.description.provenance | Made available in DSpace on 2021-05-20T20:27:04Z (GMT). No. of bitstreams: 1 ntu-97-R95922145-1.pdf: 916098 bytes, checksum: e7ed48a97ebee617a25d5a140ff32c32 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii 目錄 iv 圖目錄 vi 表目錄 viii 第1章 序論 1 第2章 背景及相關研究 3 2.1 SystemC 4 2.2 功率模組相關研究 5 第3章 SystemC模擬環境介紹 7 3.1 模擬環境及架構 7 3.1.1 應用程式模型 8 3.1.2 硬體結構模型 11 3.2 模擬正確性及速度 12 3.2.1 模擬的正確性 12 3.2.2 模擬的速度 15 3.3 小結 16 第4章 記憶體功率分析與評估 18 4.1 功率評測工具 – DRAMsim 18 4.2 應用程式位址記錄蒐集與轉換 19 4.3 應用程式功率量測 22 4.3.1 DRAMsim功率量測方法 22 4.3.2 函數層級功率量測與函數功率庫的建立 25 第5章 實驗及結果探討 29 5.1 實驗平台及步驟 30 5.2 功率量測準確度探討 32 5.2.1 Stringsearch 32 5.2.2 Susan系列 34 5.3 功率及能量消耗分析 35 第6章 結論及未來展望 39 參考文獻 41 | |
dc.language.iso | zh-TW | |
dc.title | 嵌入式計算機系統效能與功率分析之模擬環境設計 | zh_TW |
dc.title | A System-Level Performance and Power Simulation Environment for Embedded Computer Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭大維(Tei-Wei Kuo),施吉昇(Chi-Sheng Shih),周承復(Cheng-Fu Chou),林風(Phone Lin) | |
dc.subject.keyword | 行為模擬,效能分析,功率評估, | zh_TW |
dc.subject.keyword | behavioral simulation,performance analysis,power estimation, | en |
dc.relation.page | 44 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2008-08-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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