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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94435完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林致廷 | zh_TW |
| dc.contributor.advisor | Chih-Ting Lin | en |
| dc.contributor.author | 楊鈺祥 | zh_TW |
| dc.contributor.author | Yu-Hsiang Yang | en |
| dc.date.accessioned | 2024-08-15T17:28:57Z | - |
| dc.date.available | 2024-08-16 | - |
| dc.date.copyright | 2024-08-15 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-05 | - |
| dc.identifier.citation | [1]胡佳誠。「應用等效定理的電感萃取宏觀建模演算法EPRIMA」。碩士論文,國立臺灣大學電子工程學研究所,2023。
[2]R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen and L. -R. Zheng, "Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits," 2009 IEEE International Conference on 3D System Integration, San Francisco, CA, USA, 2009, pp. 1-8. [3]Wang, X.; Chen, D.; Li, D.; Kou, C.; Yang, Y. The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System. Symmetry 2023, 15, 418. [4]Z. Xu, X. Gu and J. -Q. Lu, "Parasitics extraction, wideband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging," 2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Saratoga Springs, NY, USA, 2011, pp. 1-6. [5]J. Cho et al., "Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 220-233, Feb. 2011. [6]Y. Peng, T. Song, D. Petranovic and S. K. Lim, "On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs," 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 2013, pp. 281-288. [7]J. S. Pak et al., "TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with Multi-TSV connections," 2010 IEEE CPMT Symposium Japan, Tokyo, Japan, 2010, pp. 1-4. [8]Hoer C, Love C. Exact inductance equations for rectangular conductors with applications to more complicated geometries. Journal of Research of the National Bureau of Standards–C. Engineering and Instrumentation. 1965, 69C:127137. [9]A. E. Ruehli, "Inductance Calculations in a Complex Integrated Circuit Environment," in IBM Journal of Research and Development, vol. 16, no. 5, pp. 470-481, Sept. 1972. [10]Grover F W. Inductance Calculations: Working Formulas and Tables. New York: D. Van Nostrand Company, Inc. 1947:261-282. [11]A. E. Ruehli, "Equivalent Circuit Models for Three-Dimensional Multiconductor Systems," in IEEE Transactions on Microwave Theory and Techniques, vol. 22, no. 3, pp. 216-221, Mar. 1974. [12]M. Kamon, M. J. Tsuk and J. K. White, "FASTHENRY: a multipole-accelerated 3-D inductance extraction program," in IEEE Transactions on Microwave Theory and Techniques, vol. 42, no. 9, pp. 1750-1758, Sept. 1994. [13]S. A. Schelkunoff, "Some equivalence theorems of electromagnetics and their application to radiation problems," in The Bell System Technical Journal, vol. 15, no. 1, pp. 92-112, Jan. 1936. [14]Weng Cho Chew, " Equivalence Theorem and Huygens’ Principle, " in Lectures on Electromagnetic Field Theory, pp. 157-172, 2024. [15]E. Rosa. ”The Self and Mutual Inductance of Linear Conductors”. Bull. Nat. Bur. Standards, pages 301–344, 1908. [16]Milton Abramowitz. Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables. Dover Publications, Inc.31 E. Second St. Mineola, NY, United States, 01 June 1974. [17]Clayton R. Paul, Inductance: Loop and Partial, Wiley-IEEE Press, 2009. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94435 | - |
| dc.description.abstract | 現今的封裝技術已經發展到三維堆疊的時代,各種複雜的繞線結構帶給寄生參數萃取越來越多的挑戰,電腦輔助工具需要考量到更加棘手的問題,過去可以忽視的問題逐漸需要受到正視。因此,如何快速地萃取精確(誤差小於1%)的電感參數是本作的重點。除此之外,技術與資訊的發達使得半導體產業日益競爭,如何妥善保護企業之間的商業機密亦是非常重要的議題。
主流的商業或學術軟體中的電感萃取方法都需要輸入完整的電路設計圖,因而潛在IP被竊取的風險。此外,若電路中發生某種程度上的變更,參數萃取的結果也會連帶受到影響,因此這些萃取步驟可能需要隨著變動不斷重複執行而耗費大量的時間。 基於上述的考量,我們發展出不同以往的萃取模式,我們借鑒了電磁理論中的等效原理,透過建構虛擬的等效面及邊界上的物理機制發展出新穎的演算法,可以將電路隱藏在等效面中,並在等效面的邊界上產生一組不可回溯的資料使其成為一個全新獨立的模組,在不需知道電路真實幾何結構的情況下得出精確的電感值。同時,這些建立在等效面上的模組也取代了原先大量複雜的金屬連線,降低計算的複雜度、提升後續處理的彈性。因此,我們可以透過這樣的方法有效地簡化未來先進封裝中可能帶來的挑戰。 | zh_TW |
| dc.description.abstract | The advanced packaging technology has developed into the three-dimensional stacking. The complicated routing structure brings more and more challenges to parasitic parameter extraction. Computer-aided tools need to consider more realistic issues, that could be ignored in the past become increasingly important. How to efficiently extract the accurate (less than 1%) parameters is one of the motivations for this work. In addition, the development of technology and information has made the semiconductor industry increasingly competitive. How to protect confidential commercial information is also important.
The mainstream commercial or academic software inductance extraction methods require the complete circuit layout, so there is potential risk of IP theft. In addition, if there are certain changes in the circuit, the parameters will change accordingly, the extraction steps will need to be repeated again, which might consume a lot of time. Based on the above considerations, we developed a parameter extraction macromodeling that is different from the past. We drew on the equivalence principle in electromagnetic theory to build a virtual equivalent surface and using the physical mechanism on the boundary to develop this novel algorithm. Therefore, we can hide the circuits in the equivalent surface and generate a set of non-retroactive data on the boundary to make it become an independent module. We can use this information to accurately extract the parameters without knowing the actual geometric design. Simultaneously, the information based on the equivalent surface also reduces the complexity. Therefore, we can address the challenges brought by advanced packaging in the future through this method. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-15T17:28:57Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-15T17:28:57Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES viii LIST OF TABLES xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Review 1 1.3 Our Work 3 1.4 Thesis Organization 4 Chapter 2 Preliminary 6 2.1 Maxwell’s Equations 6 2.2 Equivalence Principle 7 2.2.1 Huygens Principle 9 2.2.2 Uniqueness Theorem for Wave Equation 10 2.2.3 Equivalence Principle for Poisson's Equation 12 2.2.4 Green's Identities 17 2.3 Inductance Formulae 19 2.3.1 Partial Inductance 21 2.3.2 Self -Inductance Formulae 22 2.3.3 Mutual Inductance Formulae 23 Chapter 3 Hierarchical Inductance Macro-modeling 27 3.1 Review of Equivalence Principle for Time Harmonic 27 3.1.1 Equivalent Electric Surface Current 27 3.1.2 Equivalence Magnetic Surface Current 29 3.1.3 Issue about Equivalent Electric Field 30 3.2 Implementation of Equivalence Principle for Poisson’s Equation 35 3.2.1 G Functions 35 3.2.2 Line Integral Simplification 38 3.2.3 Numerical Integration 40 3.2.4 IP Encryption Scheme 42 3.3 Hierarchical Magnetostatics Macro Modeling 42 3.3.1 Bottom Level 43 3.3.2 Intermediate Level 45 3.3.3 Communication at Huygens Box 47 3.4 Linear System 48 Chapter 4 Experimental Results 51 4.1 Filamentary Current 51 4.1.1 Offset 51 4.1.2 Arbitrary Angle 52 4.1.3 Arbitrary Distance 54 4.1.4 Size of Huygens Box 55 4.1.5 Square Spiral Inductor 57 4.1.6 Octagonal Spiral Inductor 59 4.1.7 Hexagon Spiral Inductor with Octagon Spiral Inductor 61 4.1.8 TSVs Array I 63 4.1.9 TSVs Array II 65 4.2 Current with Rectangular Cross Section 67 4.2.1 Two Parallel Conductors 67 4.2.2 TSVs Array 68 4.3 HMMM Capability 69 4.3.1 Bottom Upward 69 4.3.2 Communication at Huygens box 72 Chapter 5 Conclusions and Future Work 74 5.1 Conclusions 74 5.2 Future Work 74 REFERENCE 76 APPENDIX A — Workflow 79 A.1 79 | - |
| dc.language.iso | en | - |
| dc.subject | 格林恆等式 | zh_TW |
| dc.subject | 電感 | zh_TW |
| dc.subject | 等效原理 | zh_TW |
| dc.subject | 加密 | zh_TW |
| dc.subject | 階層法 | zh_TW |
| dc.subject | 寄生萃取 | zh_TW |
| dc.subject | Equivalence principle | en |
| dc.subject | encryption | en |
| dc.subject | hierarchical method | en |
| dc.subject | inductance | en |
| dc.subject | parasitic extraction | en |
| dc.subject | Green's identities | en |
| dc.title | 利用等效原理與格林第三恆等式之階層電感宏觀建模 | zh_TW |
| dc.title | Hierarchical Inductance Macromodeling using Equivalence Principle and Green's Third Identity | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.coadvisor | 陳中平;鄭士康 | zh_TW |
| dc.contributor.coadvisor | Chung-Ping Chen;Shyh-Kang Jeng | en |
| dc.contributor.oralexamcommittee | 蔡坤諭 | zh_TW |
| dc.contributor.oralexamcommittee | Kuen-Yu Tsai | en |
| dc.subject.keyword | 等效原理,格林恆等式,階層法,加密,寄生萃取,電感, | zh_TW |
| dc.subject.keyword | Equivalence principle,Green's identities,hierarchical method,encryption,parasitic extraction,inductance, | en |
| dc.relation.page | 82 | - |
| dc.identifier.doi | 10.6342/NTU202402993 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-08-08 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
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