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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94263完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | zh_TW |
| dc.contributor.advisor | Chung-Yang Huang | en |
| dc.contributor.author | 李彥儒 | zh_TW |
| dc.contributor.author | Yen-Ju Lee | en |
| dc.date.accessioned | 2024-08-15T16:30:34Z | - |
| dc.date.available | 2024-08-16 | - |
| dc.date.copyright | 2024-08-15 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-07 | - |
| dc.identifier.citation | [1] Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, and Chung-Yang Huang. Match and replace: A functional eco engine for multierror circuit rectification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(3):467–478, 2013.
[2] Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, and Jie-Hong Roland Jiang. A robust functional eco engine by sat proof minimization and interpolation techniques. In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 729–734, 2010. [3] William Craig. Linear reasoning. a new form of the herbrand-gentzen theorem. Journal of Symbolic Logic, 22(3):250–268, 1957. [4] Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, and Chung-Yang (Ric) Huang. Interpolation-based incremental eco synthesis for multi-error logic rectification. In Proceedings of the 48th Design Automation Conference, DAC ’11, page 146–151, New York, NY, USA, 2011. Association for Computing Machinery. [5] Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, and Chung-Yang Huang. Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. In 2012 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1567–1572, 2012. [6] Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R Jiang, Alan Mishchenko, and Robert Brayton. Efficient computation of eco patch functions. In Proceedings of the 55th Annual Design Automation Conference, pages 1–6, 2018. [7] Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, and Ruchir Puri. Deltasyn: an efficient logic difference optimizer for eco synthesis. In Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD ’09, page 789–796, New York, NY, USA, 2009. Association for Computing Machinery. [8] Chia-Lin Hsieh. Semi-formal eco method. Master’s thesis, National Taiwan University, 2018. [9] Xuegong Zhou, Lingli Wang, and Alan Mishchenko. Fast adjustable npn classification using generalized symmetries. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 12(2):1–16, 2019. [10] Xuegong Zhou, Lingli Wang, and Alan Mishchenko. Fast exact npn classification by co-designing canonical form and its computation algorithm. IEEE Transactions on Computers, 69(9):1293–1307, 2020. [11] A. Kuehlmann, V. Paruthi, F. Krohm, and M.K. Ganai. Robust boolean reasoning for equivalence checking and functional property verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(12):1377–1394, 2002. [12] Alan Mishchenko, Roland Jiang, Satrajit Chatterjee, and Robert Brayton. Fraigs: Functionally reduced and-inv graphs. In International Conference on Computer Aided Design, 2004. [13] Alan Mishchenko. Berkeley logic synthesis and verification group, abc: A system for sequential synthesis and verification, release 20230216., 2 2023. Accessed: 2023-02-16. [14] D. Brand. Verification of large synthesized designs. In Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), pages 534–537, 1993. [15] Zheng Huang, Lingli Wang, Yakov Nasikovskiy, and Alan Mishchenko. Fast boolean matching based on npn classification. In 2013 International Conference on Field-Programmable Technology (FPT), pages 310–313, 2013. [16] Hadi Katebi and Igor Markov. Large-scale boolean matching. In Advanced Techniques in Logic Synthesis, Optimizations and Applications, pages 227–247. Springer, 2010. [17] Niklas Eén and Niklas. Sörensson. Translating pseudo-boolean constraints into sat. Journal on Satisfiability, Boolean Modeling and Computation, 2(1-4):1–26, 2006. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94263 | - |
| dc.description.abstract | 工程變更指令 (ECO) 在 IC 設計行業中至關重要，用於高效地解決錯誤和規格變更。儘管設計師努力創建無錯誤的設計，但角落案例和客戶驅動的變更常常需要快速更新。ECO 著重於識別和修補受影響的區域，並確保功能等效的前提下進行最小變更。
本研究通過兩階段方法來提升現有的 ECO 方法。在匹配階段，我們利用快速子電路 NPN 等效匹配來：1）通過識別易於修復的更正點來擴展輸入端邊界，2）識別輸出端邊界，解決輸出合併邊界的複雜性。在替換階段，我們通過引入偽布爾 (PB) 優化來高效回收浮動子電路，從而優化修補成本。 | zh_TW |
| dc.description.abstract | Engineering Change Order (ECO) is essential in the IC design industry for efficiently addressing bugs and specification changes. Despite efforts to create bug-free designs, corner cases and client-driven changes often necessitate quick updates. ECO focuses on identifying and patching affected areas with minimal changes to ensure functional equivalence.
This work enhances existing ECO methodologies through a two-phase approach. In the matching phase, we utilize fast sub-circuit NPN-equivalence matching to: 1) extend the input side frontier by identifying easy-to-fix rectification points, and 2) identify the output side frontier by addressing the complexity of the output merge frontier. In the replacement phase, we optimize patch costs by incorporating Pseudo-Boolean (PB) optimization to efficiently recycle the floating sub-circuit. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-15T16:30:34Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-15T16:30:34Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements i
中文摘要 ii Abstract iii Contents iv List of Figures vi List of Tables viii Denotation ix Chapter 1 Introduction 1 1.1 Related Works 1 1.2 Motivation 3 1.3 Contributions 4 Chapter 2 Preliminaries 5 2.1 Boolean Function 5 2.1.1 NPN Equivalent Functions 5 2.1.2 Function Symmetry of Boolean Function 6 2.2 And-Inverter Graph 6 2.2.1 Functionally Reduced AIG 6 2.2.2 K-Feasible Cut 7 2.2.3 An Illustrative Example 7 2.3 Functional Equivalence Checking 8 2.4 Boolean Matching and Cut Signature 9 2.5 Pseudo-Boolean Optimization 9 Chapter 3 Problem Formulation and Overview of Our ECO Flow 11 3.1 Functional ECO with Behavioral Change Guidance 11 3.1.1 Problem Formulation 11 3.1.2 Patch Generation and Application 12 3.1.3 Patch Cost Function 14 3.2 Overview of Our ECO Flow 14 Chapter 4 Proposed ECO Approach by NPN-Equivalent Circuit Matching 18 4.1 Matching Phase - Input Side Matching 18 4.2 Matching Phase - Output Side Matching 23 4.3 Replacement Phase - Patch Cost Optimization 27 4.3.1 Floating Gate Recycle by NPN-Equivalent Cut Matching 27 4.3.2 Patch Cost Minimization by Reiteration 32 Chapter 5 Experimental Result 34 5.1 Power of Reiterations 34 5.2 Combined with Synthesis Based Algorithm 35 5.3 Score Comparison with Top Ranking Teams in CAD Contest 2021 36 Chapter 6 Conclusion and Future Work 39 References 40 | - |
| dc.language.iso | en | - |
| dc.subject | 布林比對 | zh_TW |
| dc.subject | 工程改變命令 | zh_TW |
| dc.subject | 邏輯電路 | zh_TW |
| dc.subject | 等效性檢測 | zh_TW |
| dc.subject | 虛擬布林最佳化 | zh_TW |
| dc.subject | Pseudo-Boolean Optimization | en |
| dc.subject | Equivalence Checking | en |
| dc.subject | Logic Circuit | en |
| dc.subject | Boolean Matching | en |
| dc.subject | Engineering Change Order | en |
| dc.title | 利用 NPN 等效電路匹配進行工程改變命令補丁最小化 | zh_TW |
| dc.title | Functional ECO Patch Minimization by NPN-Equivalent Circuit Matching | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江介宏;黃紹倫;林彥德 | zh_TW |
| dc.contributor.oralexamcommittee | Jie-Hong Jiang;Shao-Lun Huang;Yen-Te Lin | en |
| dc.subject.keyword | 工程改變命令,布林比對,虛擬布林最佳化,等效性檢測,邏輯電路, | zh_TW |
| dc.subject.keyword | Engineering Change Order,Boolean Matching,Pseudo-Boolean Optimization,Equivalence Checking,Logic Circuit, | en |
| dc.relation.page | 42 | - |
| dc.identifier.doi | 10.6342/NTU202403494 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-08-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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