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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 胡璧合 | zh_TW |
| dc.contributor.advisor | Pi-Ho Hu | en |
| dc.contributor.author | 李文哲 | zh_TW |
| dc.contributor.author | Wen-Che Lee | en |
| dc.date.accessioned | 2024-08-15T16:18:47Z | - |
| dc.date.available | 2024-08-16 | - |
| dc.date.copyright | 2024-08-15 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-08-08 | - |
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Saitoh, " First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property," Proc. IEEE Symp. VLSI Technol., pp. 1-2, 2016. [13] H. Mulaosmanovic et al., "Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells," IEDM Tech. Dig., pp. 26, 2015. [14] S. Dunkel et al., "A FeFET based super-low-power ultra-fast embedded NVM technology for 22 nm FDSOI and beyond," IEDM Tech. Dig., pp. 19.7.1-19.7.4, 2017. [15] S. De et al., "Ultra-low power robust 3bit/cell Hf0.5Zr0.5O2 ferroelectric finFET with high endurance for advanced computing-in-memory technology," Proc. Symp. VLSI Technol., pp. 1-2, 2021. [16] H.-T. Lue, C.-J. Wu and T.-Y. Tseng, "Device modeling of ferroelectric memory field-effect transistor (FeMFET)", IEEE Trans. Electron Devices, vol. 49, no. 10, pp. 1790-1798, Oct. 2002. [17] H. Mulaosmanovic et al., "Impact of Read Operation on the Performance of HfO2-Based Ferroelectric FETs," IEEE Electron Device Letters, vol. 41, no. 9, pp. 1420-1423, 2020 [18] P. Chandra and P. B. Littlewood, "A Landau primer for ferroelectrics" in Physics of Ferroelectrics: A Modern Perspective, Heidelberg, Germany:Springer, pp. 69-116, 2007. [19] S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices," Nano Lett., vol. 8, no. 2, pp. 405-410, 2008. [20] Synopsys. TCAD-Sentaurus Device User Manual, Q-2019.12. [21] B. Jiang, P. Zurcher, R. E. Jones, S. J. Gillespie and J. C. Lee, "Computationally efficient ferroelectric capacitor model for circuit simulation," Proc. IEEE VLSI Technol., pp. 141-142, 1997. [22] N. Tasneem et al., "The impacts of ferroelectric and interfacial layer thicknesses on ferroelectric FET design," IEEE Electron Device Lett., vol. 42, no. 8, pp. 1156-1159, 2021. [23] D.-H. Min, S. Y. Kang, S.-E. Moon and S.-M. Yoon, "Impact of thickness control of Hf₀.₅Zr₀.₅O₂ films for the metal–ferroelectric–insulator–semiconductor capacitors," IEEE Electron Device Lett., vol. 40, no. 7, pp. 1032-1035, 2019. [24] F. Mo et al., "Efficient erase operation by GIDL current for 3D structure FeFETs with gate stack engineering and compact long-term retention model," IEEE J. Electron Devices Soc., vol. 10, pp. 115-122, 2022. [25] O. Prakash, K. Ni and H. Amrouch, "Ferroelectric FET threshold voltage optimization for reliable in-memory computing," Proc. IEEE Int. Rel. Phys. Symp. (IRPS), pp. 1-10, 2022. [26] Y.-S. Liu and P. Su, " Comparison of 2-D MoS2 and Si ferroelectric FET nonvolatile memories considering the trapped-charge-induced variability," IEEE Trans. Electron Devices, vol. 69, no. 5, pp. 2738-2740, 2022. [27] A. Mallick and N. Shukla, "Evaluation of bulk and SOI FeFET architecture for non-volatile memory applications," IEEE J. Electron Devices Soc., vol. 7, pp. 425-429, 2019. [28] V. P.-H. Hu, P.-C. Chiu and Y.-C. Lu, "Impact of work function variation line-edge roughness and ferroelectric properties variation on negative capacitance FETs," IEEE J. Electron Devices Soc., vol. 7, pp. 295-302, 2019.. [29] G. Choe and S. Yu, "Variability study of ferroelectric field-effect transistors towards 7 nm technology node," IEEE J. Electron Devices Soc., vol. 9, pp. 1131-1136, 2021. [30] Y.-S. Liu and P. Su, "Variability analysis for ferroelectric FET nonvolatile memories considering random ferroelectric-dielectric phase distribution," IEEE Electron Device Lett., vol. 41, no. 3, pp. 369-372, 2020. [31] Y.-S. Liu and P. Su, "Impact of trapped-charge variations on scaled ferroelectric FET nonvolatile memories," IEEE Trans. Electron Devices, vol. 68, no. 4, pp. 1639-1643, 2021. [32] C. Garg et al., "Impact of random spatial fluctuation in non-uniform crystalline phases on the device variation of ferroelectric FET," IEEE Electron Device Lett., vol. 42, no. 8, pp. 1160-1163, 2021. [33] S. Lee et al., "Effect of floating gate insertion on the analog states of ferroelectric field-effect transistors," IEEE Trans. Electron Devices, vol. 70, no. 1, pp. 349-353, 2023. [34] "International Roadmap for Devices and Systems (IRDS)," 2017. [35] K. Lee, S. Kim, M. Kim, J.-H. Lee, D. Kwon and B.-G. Park, "Comprehensive TCAD-based validation of interface trap-assisted ferroelectric polarization in ferroelectric-gate field-effect transistor memory," IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1048-1053, 2022. [36] K. Lee, S. Kim, M. Kim, J.-H. Lee, D. Kwon and B.-G. Park, "Comprehensive TCAD-based validation of interface trap-assisted ferroelectric polarization in ferroelectric-gate field-effect transistor memory," IEEE Trans. Electron. Devices, vol. 69, no. 3, pp. 1048-1053, 2022. [37] S. Deng, Z. Liu, X. Li, T. P. Ma and K. Ni, "Guidelines for ferroelectric FET reliability optimization: Charge matching," IEEE Electron Device Lett., vol. 41, no. 9, pp. 1348-1351, 2020. [38] A. Bansal, B. C. Paul and K. Roy, "Modeling and optimization of fringe capacitance of nanoscale DGMOS devices," IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 256-262, 2005. [39] R. Cao et al., "Effects of capping electrode on ferroelectric properties of Hf0.5Zr0.5O2 thin films," IEEE Electron Device Lett., vol. 39, no. 8, pp. 1207-1210, 2018. [40] T. Ali et al., "A multilevel FeFET memory device based on laminated HSO and HZO ferroelectric layers for high-density storage," IEDM Tech. Dig., pp. 7-28, 2019. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/94224 | - |
| dc.description.abstract | 鐵電場效電晶體(ferroelectric field-effect transistor, FeFET)作為新興記憶體，具有非揮發性、與CMOS製程相容等優點，並且可以通過鐵電材料的特性實現多位元儲存功能，因此被認為是極具潛力的記憶體技術。然而，鐵電場效電晶體在實際應用中仍面臨元件變異度影響和提升記憶體視窗(memory window, MW)的挑戰。為了解決這些問題，本論文致力於研究如何降低鐵電場效電晶體的變異度並增大其記憶體視窗。
首先，本論文研究了負交疊(underlap)和正交疊(overlap)設計對bulk和SOI基板上鰭式鐵電場效電晶體(FeFinFET)之記憶體性能影響。研究結果顯示，在bulk基板上，相較於正交疊設計，採用負交疊設計的鰭式鐵電場效電晶體可以提高6.7%的記憶體視窗。然而，在使用SOI基板的鰭式鐵電場效電晶體中，負交疊設計反而會使記憶體視窗下降，因此，對於SOI基板，正交疊設計是必要的。此外，我們還發現，對於傳統平面(planar)結構的鐵電場效電晶體(FeFET)，其趨勢與bulk基板上的鰭式鐵電場效電晶體相同，因此，對於使用bulk基板的FeFET而言，負交疊設計可以幫助我們在抹除時在通道產生更多的電洞，來幫助鐵電層抹除的更好，從而提高記憶體視窗。 接著，本論文探討了在隨機相位分佈(random phase distribution)條件下，金屬閘極功函數對鐵電場效電晶體間變異度的影響。結果顯示，隨著功函數的增加，高臨界電壓狀態的變異度增大，而低臨界電壓狀態的變異度減小。此外，為了更全面研究不同鐵電相比例下的優化策略，本論文探討了功函數與記憶體視窗平均值(μMW)和標準差(σMW)之間的關聯。研究發現，較高的功函數雖然降低了μMW，但卻能更有效地抑制σMW。然而，這種效應在高鐵電相比例(如含有75%鐵電相元件，FE = 75%)時不那麼顯著。因此，對於鐵電相比例較低的FeFET(如鐵電相小於50%的元件，FE ≤ 50%)，我們傾向於使用較高的功函數(如5.25 eV)以達到更高的μMW/σMW值；相反，對於鐵電相比例較高的鐵電場效電晶體而言(如含有75%鐵電相元件，FE = 75%)，選擇較低的功函數(如4.25 eV)更為適宜。 此外，本論文結合負交疊設計對元件性能進行評估。觀察結果顯示，當功函數大於4.25 eV時，隨著負交疊長度的增加，σMW顯著降低改善，尤其在功函數為5.25 eV時達到最大改善幅度，且這一優勢同樣適用於高鐵電相比例的鐵電場效電晶體(如含有75%鐵電相元件，FE = 75%)。因此，使用負交疊設計後，無論鐵電相比例高低，我們都傾向於使用較高的功函數(如5.25 eV)以達到更高的μMW/σMW值。 | zh_TW |
| dc.description.abstract | Ferroelectric field-effect transistors (FeFETs) are emerging as promising memory technologies due to their non-volatility, compatibility with CMOS processes, and capability to achieve multi-bit storage through the unique properties of ferroelectric materials. However, practical applications of FeFETs face significant challenges, particularly regarding device variability and enhancing the memory window (MW). This thesis addresses these challenges by exploring methods to reduce FeFET variability and increase the MW.
Firstly, this paper explores the impact of underlap and overlap designs on the memory performance of FeFinFETs on both bulk and SOI substrates. The MW is utilized as the primary electrical indicator for FeFETs. The study reveals that, on bulk substrates, FeFinFETs with underlap designs exhibit a 6.7% increase in MW compared to those with overlap designs. Conversely, for FeFinFETs on SOI substrates, underlap designs result in a reduced MW, indicating that overlap designs are necessary for SOI substrates. Additionally, we found that for conventional planar FeFETs, the trends are consistent with those observed in FeFinFETs on bulk substrates. This is because, for FeFETs on bulk substrates, the underlap design can help generate more holes during the erase operation, aiding in better ferroelectric layer erasing and increasing the MW. Subsequently, the paper investigates the effect of the metal gate work function on FeFET variability considering random phase distribution. Results show that as the work function increases, the variability in the high threshold voltage state increases, while the variability in the low threshold voltage state decreases. This thesis examines the impact of work function on the mean value and standard deviation of MW (μMW and σMW) under different ferroelectric phase percentages to develop a comprehensive optimization strategy. Our results show that a higher work function, although it reduces μMW, is more effective in suppressing σMW. However, this effect is less pronounced at higher ferroelectric phase percentages (FE = 75%). Therefore, a higher work function (5.25 eV, for example) is preferred for FeFETs with a lower ferroelectric phase percentage (FE ≤ 50%) to achieve a higher μMW/σMW ratio. Conversely, a lower work function (4.25 eV, for example) is more suitable for FeFETs with a higher ferroelectric phase percentage (FE = 75%). Furthermore, this study evaluates the performance of devices with underlap designs while considering the effects of random phase distribution. Observations indicate that when the work function exceeds 4.25 eV, increasing the underlap distance significantly improves σMW, with the maximum improvement observed at a work function of 5.25 eV. This advantage also applies to FeFETs with a high ferroelectric phase percentage (FE = 75%). Consequently, after employing underlap designs, a higher work function (5.25 eV, for example) is preferred to achieve a higher μMW/σMW ratio, regardless of the ferroelectric phase percentage. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-15T16:18:47Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-15T16:18:47Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 I
摘要 II Abstract IV 目次 VI 圖次 VIII 表次 XIII 第一章 導論 1 1.1 非揮發性記憶體 1 1.2 鐵電性 3 1.2.1 鐵電性的起源 3 1.2.2 鐵電性材料 4 1.2.3 鐵電記憶體種類 6 1.3 鐵電場效電晶體 9 1.3.1 操作原理 9 1.3.2 記憶體視窗 11 1.3.3 鐵電行為模型之介紹 12 1.4 記憶體視窗優化之設計 15 1.4.1 正交疊與負交疊 15 1.4.2 金屬功函數之選擇 17 1.5 鐵電場效電晶體之變異度 18 1.6 研究動機 21 1.7 論文架構 22 第二章 利用正交疊和負交疊設計優化記憶體視窗 23 2.1 前言 23 2.2 元件結構與模擬參數 24 2.3 鰭式鐵電場效電晶體記憶體視窗之分析 27 2.4 對於傳統平面結構鐵電場效電晶體記憶體視窗之分析 35 2.5 結論 36 第三章 透過功函數工程改善記憶體視窗之變異度 37 3.1 前言 37 3.2 元件結構與模擬參數 38 3.3 對於不同鐵電百分比元件之影響 40 3.4 結合負交疊設計對元件表現之影響 51 3.5 結論 56 第四章 總結與未來展望 57 4.1 總結 57 4.2 未來展望 59 參考文獻 60 | - |
| dc.language.iso | zh_TW | - |
| dc.subject | 鐵電場效電晶體 | zh_TW |
| dc.subject | 正交疊與負交疊設計 | zh_TW |
| dc.subject | 記憶體視窗 | zh_TW |
| dc.subject | 金屬功函數 | zh_TW |
| dc.subject | 變異度 | zh_TW |
| dc.subject | metal work function | en |
| dc.subject | ferroelectric field-effect transistor | en |
| dc.subject | underlap and overlap designs | en |
| dc.subject | variability | en |
| dc.subject | memory window | en |
| dc.title | 透過負交疊技術及功函數工程改善鐵電場效電晶體之變異度分析 | zh_TW |
| dc.title | Reduced Variability of Ferroelectric Field-Effect Transistors on Bulk Substrate through Underlap Design and Work Function Engineering | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 胡振國;蘇俊榮 | zh_TW |
| dc.contributor.oralexamcommittee | Jenn-Gwo Hwu;Chun-Jung Su | en |
| dc.subject.keyword | 鐵電場效電晶體,正交疊與負交疊設計,記憶體視窗,金屬功函數,變異度, | zh_TW |
| dc.subject.keyword | ferroelectric field-effect transistor,underlap and overlap designs,memory window,metal work function,variability, | en |
| dc.relation.page | 63 | - |
| dc.identifier.doi | 10.6342/NTU202403782 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-08-12 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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