應用有限體積法進行非曼哈頓封裝與片上電阻萃取

Abstract

科技發展日新月異，各式電路的複雜度日趨上升，進而使封裝技術成為一大注目焦點。尤其是非曼哈頓封裝，允許在各種角度進行佈局走線，其靈活性雖然提高了設計效率，但也增加了電性計算的難度。隨著電路設計向高密度和高性能方向發展，如何精確地計算非曼哈頓封裝中的電阻成為一個重要課題。 基於以上的重點，我們提出了一種新的演算法來計算非曼哈頓封裝中的片上電阻，旨在降低電路電阻計算的複雜性，同時觀察該電路的電壓分布變化以及電流電場的流向。該演算法的核心思想是通過將電路導體的表面分割為單位網格的座標，然後結合有限體積法來進行分析。 該演算法，根據座標將電路導體的表面分割為單位網格，接著結合有限體積法，我們能得知每一個網格點之間的電壓關係式，進而組織出一個完整電路的大型電壓運算矩陣，由此推導出導體的電壓分布，最終推導出電流值，以計算總電阻值。

The rapid advancement of technology has led to increasing complexity in various circuits, making packaging technology a significant focus of attention. Non-Manhattan packaging, in particular, allows for routing at various angles, which enhances design flexibility but also increases the difficulty of electrical calculations. As circuit design trends towards higher density and performance, calculating the resistance in non-Manhattan packaging has become a critical issue. To address this, we propose a new algorithm to calculate the on-chip resistance in non-Manhattan packaging, aiming to reduce the complexity of resistance calculations while observing voltage distribution and current field directions on conductor. The core idea of this algorithm is to divide the surface of conductor into unit grid coordinates and then analyze it using the Finite Volume Method. By dividing the surface of the conductor into unit grids based on coordinates and combining with the Finite Volume Method, we determine the voltage relationships between each grid point. This allows us to construct a global matrix for the entire circuit. By solving this matrix, we derive the voltage distribution on the conductor, and subsequently, calculate the current values to determine the total resistance.