真實量子電腦的測試與錯誤緩解

Abstract

近年來，大量多位元量子電腦成功備製造，量子計算領域有相當的進步。然而，量子電腦系統中可能會由於量子態和量子位元中不可避免的干擾而發生錯誤。因為量子位元不僅可以改變其0或1的值，還可以改變相位或糾纏，所以這些錯誤比經典的位元錯誤更複雜。為了處理這些錯誤，我們需要錯誤檢測和處理技術。 在這篇論文中，我介紹了適用於真實量子電腦測試和減少錯誤的三個實際進展。首先，我介紹如何對量子電腦中的故障進行建模。我們根據量子點元件的實際物理現象提出了六種故障模型。這些故障模型透過哈密頓模擬進行模擬，因此它們可以代表真實的缺陷行為並控制故障。這些故障模型可用於量子電路中的可擴展故障檢測和緩解。 其次，我介紹了使用網格搜尋和梯度下降來產生線上測試量子電路。我們修改 qATG 以產生線上測試電路，在單一次量測中檢測多個故障。因此，透過線上測試進行即時量子錯誤檢測是可行的。然後，我透過線上測試和後選擇來緩解錯誤。利用IBM Q的動態電路功能，我們的錯誤緩解技術能夠緩解在幾次執行時間內保持不變的錯誤。結果表明，我們的方法顯著減少了 IBM Q 真實設備上的錯誤。 最後，我提出了三種改進機率錯誤消除(PEC)的方法。我們提出了解決 PEC 兩個問題的方法：(1)目前還沒有針對參數化量子邏輯閘的有效PEC方法。(2)隨著透過PEC緩解錯誤的量子邏輯閘數量增加，所需的採樣開銷呈指數增加。我們的參數化邏輯閘PEC(PGPEC)擴展了PEC的功能，使其透過內插法適用於參數化閘。我們的巨集邏輯閘PEC(MGPEC)將多個量子閘合併為一個巨集邏輯閘，因此減少了PEC取樣開銷的指數項。我們的設計多樣性PEC(DDPEC)使用設計多樣性來減少採樣開銷的指數基數。結合這些技術可以顯著降低PEC的整體採樣開銷。本論文是在考慮現實條件的狀況下開發測試和錯誤緩解方面的開拓性研究之一。

Quantum computing has advanced much in recent years. However, errors in quantum computer systems can occur due to unavoidable disturbances, such as faults, in the quantum state and quantum bits (qubits). These errors are more complex than classical bit errors, as qubits can not only change their zero or one value but also change a phase or entanglement. To handle these errors, we need error detection and handling techniques. In this thesis, I present three practical advancements in testing and mitigating errors in realistic quantum computers. First, I present how to model faults in a realistic quantum circuit. We proposed six fault models derived from the actual physical phenomenon of quantum dot devices. These fault models are simulated by Hamiltonian simulation so they can represent true defect behavior and control faults. These fault models can be used for scalable fault detection and mitigation in quantum circuits. Second, I present the application of grid search and gradient descent to generate online test quantum circuits. We modify the qATG to generate online test circuits that detect multiple faults in a single shot. Hence, Real-time quantum error detection through online testing is feasible. Then, I present error mitigation via online testing and post-selection. Utilizing the dynamic circuit of IBM Q, our error mitigation technique is capable of mitigating faults that remain constant over a few shots. The result shows that it significantly reduces the error on IBM Q real devices. Finally, I present three methods to improve probabilistic error cancellation (PEC), an error mitigation method that represents ideal operations as linear combinations of noisy operations. We propose methods to resolve two issues of PEC: (1) There is currently no effective PEC approach available for parameterized gates. (2) The sampling overhead increases exponentially as the number of PEC-mitigated gates increases. Our parameterized gate PEC (PGPEC) extends the capability of PEC so that it works for parameterized gates via interpolation. Our macro gate PEC (MGPEC) merges multiple quantum gates into a macro gate so the exponent of PEC sampling overhead is reduced. Our design diversity PEC (DDPEC) uses design diversity to reduce the exponential bases of the sampling overhead. Combining these techniques can significantly reduce the overall sampling overhead of PEC. This thesis is one of the pioneering works in quantum computer testing and error mitigation that considers realistic constraints.