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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93898完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭斯彥 | zh_TW |
| dc.contributor.advisor | Sy-Yen Kuo | en |
| dc.contributor.author | 洪世昌 | zh_TW |
| dc.contributor.author | Shih-Chang Hung | en |
| dc.date.accessioned | 2024-08-09T16:17:08Z | - |
| dc.date.available | 2024-08-10 | - |
| dc.date.copyright | 2024-08-09 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-31 | - |
| dc.identifier.citation | [1] Kai-Hui Chang and Chris Browy. Improving gate-level simulation accuracy when unknowns exist. In Proceedings of the 49th Annual Design Automation Conference, pages 936–940, 2012.
[2] Kai-Hui Chang, Yen-Ting Liu, and Chris Browy. Automated methods for eliminating x bugs. In Fifteenth International Symposium on Quality Electronic Design, pages 597–603. IEEE, 2014. [3] Ieee standard for verilog hardware description language. IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001), page 108, 2006. [4] 卓旻科. 使⽤模式匹配及對稱性解析單位元件功能. Master’s thesis, 國立臺灣大學, Jan 2016. [5] Tommi Junttila and Petteri Kaski. Engineering an efficient canonical labeling tool for large and sparse graphs. In 2007 Proceedings of the Ninth Workshop on Algorithm Engineering and Experiments (ALENEX), pages 135–149. SIAM, 2007. [6] Randal E Bryant. Graph-based algorithms for boolean function manipulation. Computers, IEEE Transactions on, 100(8):677–691, 1986. [7] Robert Brayton and Alan Mishchenko. Abc: An academic industrial-strength verification tool. In Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings 22, pages 24–40. Springer, 2010. [8] Fabio Somenzi. Cudd: Cu decision diagram package. Public Software, University of Colorado, 1997. [9] James E. Stine, Ivan Castellanos, Michael Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, and Ravi Jenkal. Freepdk: An open-source variation-aware design kit. In 2007 IEEE International Conference on Microelectronic Systems Education (MSE’07), pages 173–174, 2007. [10] Globalfoundries gf180mcu open source pdk. [Online] Available: https://github.com/google/gf180mcu-pdk. [11] Skywater open source pdk. [Online] Available: https://github.com/google/skywater-pdk. [12] C. Y. Lee. Representation of switching circuits by binary-decision programs. The Bell System Technical Journal, 38(4):985–999, 1959. [13] Sheng Yang, Bashir M Al-Hashimi, David Flynn, and Saqib Khursheed. Scan based methodology for reliable state retention power gating designs. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pages 69–74. IEEE, 2010. [14] Richard Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), pages 42–47. IEEE, 1993. [15] David Gries and Fred B Schneider. A logical approach to discrete math. Springer Science & Business Media, 2013. [16] Beate Bollig and Ingo Wegener. Improving the variable ordering of obdds is np-complete. IEEE Transactions on computers, 45(9):993–1002, 1996. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93898 | - |
| dc.description.abstract | 在數位設計中,未知值(X)的存在可能會導致誤解,導致X悲觀主義和X樂觀主義,這可能會誤導設計人員並導致不必要的調試工作。為了緩解這些問題,對使用者定義基元進行全面的引腳識別的需求日益明顯。我們提出了一種結合啟發式方法、結構感知技術和二元決策圖 (BDD) 的方法。
我們的方法旨在識別和理解設計中引腳/輸入的行為,從而實現更準確的分析和最佳化。具體來說,我們採用啟發式模式匹配方法來區分閂鎖、正反器和具有多個選擇/啟用功能的單元。 此外,我們探索了 二元決策圖 的應用來有效地表示和操縱設計的邏輯,促進徹底的分析和最佳化,從而提高工業單元庫的辨識度。大規模商業設計的實驗結果證明了我們提出的方法在解決引腳功能識別問題方面的有效性和效率,從而提高了數位設計的可靠性和正確性。 | zh_TW |
| dc.description.abstract | In digital design, the presence of unknown values (Xs) can lead to misinterpretations, resulting in X-pessimism and X-optimism, which may misguide designers and lead to unnecessary debugging efforts. To mitigate these issues, the need for a comprehensive pin recognition for user-defined primitives is increasingly apparent. We proposed an approach that combines heuristic methods, structure-aware techniques, and the utilization of Binary Decision Diagrams (BDDs).
Our approach aims to identify and understand the behavior of pins/inputs within the design, enabling more accurate analysis and optimization. Specifically, we employ heuristic pattern matching methods to distinguish between normal latches, flip-flops, and cells with multiple select/enable functions. Furthermore, we explore the application of BDDs to efficiently represent and manipulate the logic of the design, facilitating thorough analysis and optimization, which improves the recognition of industrial cell libraries. Experimental results on commercial designs demonstrate the effectiveness and efficiency of our proposed methods in addressing pin function recognition problem, thereby improving the reliability and correctness of digital designs. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-09T16:17:08Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-08-09T16:17:08Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii 1 Introduction 1 2 Preliminary 4 2.1 Unknown Value(X) 4 2.2 False-X bugs 5 2.3 Binary Decision Diagrams (BDDs) 6 2.4 Simxact 8 2.5 User-Defined Primitives 9 3 Algorithm 12 3.1 Problem description 12 3.2 Algorithm Overview 12 3.3 Pattern Matching and Dominating Pin Identification 14 3.4 Handling Asymmetric Tables with BDD Variable Reordering 15 3.5 SUDP Pin Analysis Algorithm Breakdown 19 4 Experimental Results 27 4.1 Test Setup 27 4.2 Analysis of Results 28 5 Conclusion 31 Bibliography 32 | - |
| dc.language.iso | en | - |
| dc.subject | 二元決策圖 | zh_TW |
| dc.subject | 未知值 | zh_TW |
| dc.subject | 篩選算法 | zh_TW |
| dc.subject | 引腳識別 | zh_TW |
| dc.subject | 啟發式演算法 | zh_TW |
| dc.subject | Binary Decision Diagram | en |
| dc.subject | Heuristic Method | en |
| dc.subject | Unknown Value | en |
| dc.subject | Digital Design | en |
| dc.subject | Pin Identification | en |
| dc.title | 以模式配對及二元決策圖從序向真值表重建單元邏輯電路之功能 | zh_TW |
| dc.title | Reconstructing Cell Functions from Sequential Truth Tables Using Pattern Matching and Binary Decision Diagram | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 雷欽隆;呂學坤;林宗男;袁世一 | zh_TW |
| dc.contributor.oralexamcommittee | Chin-Laung Lei;Shyue-Kung Lu;Tsung-Nan Lin;Shih-Yi Yuan | en |
| dc.subject.keyword | 二元決策圖,引腳識別,篩選算法,未知值,啟發式演算法, | zh_TW |
| dc.subject.keyword | Binary Decision Diagram,Pin Identification,Digital Design,Unknown Value,Heuristic Method, | en |
| dc.relation.page | 33 | - |
| dc.identifier.doi | 10.6342/NTU202402119 | - |
| dc.rights.note | 同意授權(限校園內公開) | - |
| dc.date.accepted | 2024-08-02 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-07-29 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
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