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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93530
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor郭斯彥zh_TW
dc.contributor.advisorSy-Yen Kuoen
dc.contributor.author黃詩瑜zh_TW
dc.contributor.authorShih-Yu Huangen
dc.date.accessioned2024-08-05T16:23:19Z-
dc.date.available2024-08-06-
dc.date.copyright2024-08-05-
dc.date.issued2024-
dc.date.submitted2024-07-17-
dc.identifier.citation[1] C. R. V. R. Gaurav Tembey, Adriana Dahik, “Navigating the Costly Economics of Chip Making,” Boston Consulting Group, Tech. Rep., 2023. [Online]. Available: https://www.bcg.com/publications/2023/ navigating-the-semiconductor-manufacturing-costs
[2] A. Meyer, Principles of Functional Verification. Newnes, 2003.
[3] H. Foster, “Part 12: The 2022 Wilson Research Group Functional Verification Study,” Siemens, Tech. Rep., 2023. [Online]. Available: https://blogs.sw.siemens.com/verificationhorizons/2023/01/09/part-12-the-2020-wilson-research-group-functional-verification-study-2/
[4] “IEEE Draft Standard for Ethernet,” IEEE P802.3/D3.0, November 2017 (Revision of IEEE Std 802.3-2015), pp. 1–5261, 2017.
[5] N. JAIN, “PAM & Ethernet: A Perfect Match,” 2016. [Online]. Available: https://www.edn.com/pam-ethernet-a-perfect-match/
[6] A. KALNOSKAS, “The ABCs of functional verification techniques,” 2021. [Online]. Available: https://www.analogictips.com/what-are-abcs-of-functional-verification-techniques/
[7] B. Kiani, “Static verification is key to complex chip design,” 1999. [Online]. Available: https://www.eetimes.com/static-verification-is-key-to-complex-chip-design/
[8] A. Fatima, “Introduction to Formal Verification,” 2019. [Online]. Available: https://www.eeweb.com/introduction-to-formal-verification/
[9] N. B. Harshitha, Y. G. Praveen Kumar, and M. Z. Kurian, “An Introduction to Universal Verification Methodology for the digital design of Integrated circuits (IC's): A Review,” in 2021 International Conference on Artificial Intelligence and Smart Systems (ICAIS), 2021, pp. 1710–1713.
[10] H. Foster, “Part 10: The 2022 Wilson Research Group Functional Verification Study,” Siemens, Tech. Rep., 2022. [Online]. Available: https://blogs.sw.siemens.com/verificationhorizons/2022/12/26/strongpart-10-the-2022-wilson-research-group-functional-verification-study-strong/
[11] K. Salah, “A UVM-based smart functional verification platform: Concepts, pros, cons, and opportunities,” in 2014 9th International Design and Test Symposium (IDT), 2014, pp. 94–99.
[12] T.Kawauchi, A.Iwata, H.Urayama, T.Izumi, K.Takayama, and T.Hagihara, “Physical Layer Simulation Technology for Automotive Ethernet,” in 2019 IEEE CPMT Symposium Japan (ICSJ), 2019, pp. 107–110.
[13] P. N. Karthik and K. Suresh, “Devise and establishment of property specification language to verify the complex behaviour of FPGA Ethernet IP core,” in 2016 IEEE International Conference on Recent Trends in Electronics, Information Communication Technology (RTEICT), 2016, pp. 763–768.
[14] J. Tonfat, G. Neuberger, and R. Reis, “Functional verification of logic modules for a Gigabit Ethernet switch,” in 2011 12th Latin American Test Workshop (LATW), 2011, pp. 1–4.
[15] M.Qian, J.Zhu, Y.Cao, and C.Yang, “Design and FPGA Verification of Dual-Speed Adaptive Ethernet Controller,” in 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing, 2011, pp. 1–3.
[16] S. Chitti, P. Chandrasekhar, and M. Asha Rani, “Gigabit Ethernet verification using efficient verification methodology,” in 2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015, pp. 1231–1235.
[17] C. Jenila, S. K. R. Gurram, L. C. Jagarlamudi, M. S. S. R. Kota, and S. P. Kasthala, “Verification of 10 GB Ethernet MAC Core using Loopback Bringup Testcase,” in 2023 7th International Conference on Intelligent Computing and Control Systems (ICICCS), 2023, pp. 1769–1774.
[18] M. Charyulu, N. M. Kanth, and V. S. Kushwah, “UVM Based Verification of an Ethernet MAC using Wishbone Bus,” in 2024 IEEE 13th International Conference on Communication Systems and Network Technologies (CSNT), 2024, pp. 183–188.
[19] M. Chinchole and K. Kinage, “Functional Verification of Ten Gigabytes Media Independent Interface (XGMII) Using Universal Verification Methodology,” in 2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA), 2018, pp. 1–4.
[20] R. Fischer, C. Windpassinger, A. Lampe, and J. Huber, “Tomlinson-Harashima precoding in space-time transmission for low-rate backward channel,” in 2002 International Zurich Seminar on Broadband Communications Access - Transmission - Networking (Cat. No.02TH8599), 2002, pp. 7–7.
[21] Y.-R. Chien, Y.-T. Tu, H.-W. Tsao, and W.-L. Mao, “Equalization and Interference Cancellation with MIMO THP for 10GBASE-T,” in 2007 IEEE Workshop on Signal Processing Systems, 2007, pp. 95–100.
[22] Y. Tao, “An introduction to assertion-based verification,” in 2009 IEEE 8th International Conference on ASIC, 2009, pp. 1318–1323.
[23] R. A. Marat Teplitsky, Amit Metodi, “Coverage Driven Distribution of Constrained Random Stimuli,” Cadence Design Systems, Tech. Rep., 2014.
[24] Y. Wu, L. Yu, W. Zhuang, and J. Wang, “A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit,” in 2009 Eighth IEEE/ACIS International Conference on Computer and Information Science, 2009, pp. 1049– 1054.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93530-
dc.description.abstract乙太網路為目前區域網路中使用最廣泛的有線電腦網路技術之一,由IEEE組織制定的802.3標準所規範。其速度規格從最初投入市場的10Mbps逐漸發展至目前的1.6Tbps,乙太網路憑藉其高速傳輸能力,積極滿足快速擴展的頻寬需求以應對不斷增加的數據流量的挑戰。在乙太網路複雜的架構中,為了提高整體傳輸質量,其對資料處理採用了各種通訊編碼。隨著晶片和電路的複雜性增加,我們必須確保電路的正確性符合規格要求,因此驗證技術變得不可或缺。

本研究旨在開發一個有效的乙太網路驗證環境,透過對功能性驗證的深入研究,提出了一套針對2.5GBASE-T乙太網路的驗證方法和平台。該方法使用斷言的驗證技術,透過收集覆蓋率來評估驗證的完整性。同時,我們使用SystemVerilog語言建立UVM(Universal Verification Methodology)驗證環境,UVM是一種具有標準化和模組化架構的驗證框架,可以進行模擬和驗證複雜的硬件系統,有助於高效的檢驗乙太網路的功能性並提高覆蓋率。

論文中詳細闡述了測試案例設計流程和乙太網路驗證流程以及針對2.5GBASE-T所設計的UVM驗證平台,透過建構60個斷言和41個測試案例進行模擬,實驗結果顯示覆蓋率達到100%,表明該驗證平台能夠確保以太網路的正常運行,並且符合規範。本研究的貢獻有助於為乙太網路提供可靠性。
zh_TW
dc.description.abstractEthernet is one of the most widely used wired computer network technologies in current local area networks, regulated by the IEEE 802.3 standard. Its speed specifications have evolved from the initial 10Mbps to the current 1.6Tbps. With its high-speed transmission capabilities, Ethernet effectively meets the rapidly expanding bandwidth requirements, addressing the challenges of increasing data traffic. To enhance overall transmission quality within Ethernet's complex architecture, various communication encodings are employed for data processing. As chip and circuit complexity increases, verification techniques become indispensable to ensure that circuit correctness meets specification requirements.

This paper aims to develop an effective Ethernet verification environment. Through an in-depth study of functional verification, we propose a set of verification methods and platforms for 2.5GBASE-T Ethernet. This approach employs assertion verification technology to evaluate the completeness of verification by collecting coverage data. Additionally, we utilize the SystemVerilog language to establish a UVM (Universal Verification Methodology) verification environment. UVM is a standardized, modular verification framework that can simulate and verify complex hardware systems, thereby helping to efficiently verify Ethernet functionalities and improve coverage.

The paper details the test case design processes and Ethernet verification processes, as well as the UVM verification platform designed for 2.5GBASE-T. By constructing 60 assertions and 41 test cases for simulation, the experimental results show a coverage rate of 100%, indicating that the verification platform we established can ensure the Ethernet network operates correctly and meets specifications. The contributions of this research enhance the reliability of Ethernet.
en
dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-05T16:23:19Z
No. of bitstreams: 0
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dc.description.provenanceMade available in DSpace on 2024-08-05T16:23:19Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontents誌謝 i
摘要 ii
Abstract iii
Contents v
List of Figures viii
List of Tables ix
Chapter 1 Introduction 1
Chapter 2 Background 3
2.1 Ethernet Architecture 3
2.1.1 MAC 5
2.1.2 RS 7
2.1.3 MII 7
2.1.4 PCS 7
2.1.5 PMA 8
2.1.6 AN 8
2.2 Verification 9
2.2.1 Static Verification 10
2.2.2 Functional Simulation 11
2.2.3 FPGA Prototyping 11
2.2.4 UVM 12
2.3 Previous Work of Ethernet Verification 14
Chapter 3 2.5GBASE-T Ethernet 16
3.1 The Architecture of 2.5GBASE-T Ethernet 16
3.2 Operation of 2.5GBASE-T Ethernet 17
3.3 Physical Coding Sublayer(PCS) 19
3.3.1 Normal Mode 19
3.3.2 Training Mode 23
3.4 Physical Medium Attachment (PMA) Sublayer 23
3.4.1 Normal Mode 23
3.4.2 Training Mode 24
Chapter 4 Verification Methodology 26
4.1 Assertion-based Verification 26
4.2 Coverage-Driven Verification 28
4.3 Verification Component 29
4.3.1 Configuration Database 30
4.3.2 Monitor 31
4.3.3 Sequence Item 31
4.3.4 Sequence 33
4.3.5 Sequencer 33
4.3.6 Driver 34
4.3.7 Agent 35
4.3.8 Reference Model 36
4.3.9 Scoreboard 36
4.3.10 Environment 36
4.3.11 Test Case 37
4.4 Verification Platform Architecture 37
4.5 Verification Flow 38
Chapter 5 Experimental Result 41
5.1 Verification Environment Structure 41
5.2 Test Cases and Assertions Distribution 42
5.3 Comparison with Previous Research 43
Chapter 6 Conclusion 45
References 47
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dc.language.isoen-
dc.subject乙太網路zh_TW
dc.subject驗證zh_TW
dc.subject覆蓋率zh_TW
dc.subject斷言zh_TW
dc.subject通用驗證方法學zh_TW
dc.subjectuniversal verification methodologyen
dc.subjectassertionen
dc.subjectcoverageen
dc.subjectetherneten
dc.subjectverificationen
dc.title基於斷言的 2.5GBASE-T 以太網路 UVM 驗證平台之高效設計與實現zh_TW
dc.titleEfficient Design and Implementation of an Assertion-Based UVM Verification Platform for 2.5GBASE-T Etherneten
dc.typeThesis-
dc.date.schoolyear112-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee林宗男;雷欽隆;袁世一;呂學坤zh_TW
dc.contributor.oralexamcommitteeTsung-Nan Lin;Chin-Laung Lei;Shih-Yi Yuan;Shyue-Kung Luen
dc.subject.keyword驗證,乙太網路,通用驗證方法學,斷言,覆蓋率,zh_TW
dc.subject.keywordverification,ethernet,universal verification methodology,assertion,coverage,en
dc.relation.page50-
dc.identifier.doi10.6342/NTU202401830-
dc.rights.note同意授權(限校園內公開)-
dc.date.accepted2024-07-18-
dc.contributor.author-college電機資訊學院-
dc.contributor.author-dept電子工程學研究所-
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