一個使用有限脈衝響應濾波器回授之13.6有效位元基於電壓控制振盪器之二階連續時間三角積分調變器

Abstract

在本論文中提出了一種基於轉導電容式積分器和壓控振盪器的二階電容耦合連續時間Δ-Σ調製器，用於閉環神經記錄傳感器讀取。 這種方法消除了在前端電路中使用低雜訊放大器和類比數位轉換器的需求。而是直接透過使用高解析度的Δ-Σ調變器當作完整的感測器前端電路。並通過在第二級使用壓控振盪器作為量化器，經過動態元素匹配處理後的數位輸出增加了數位類比轉換器的線性度，從而無需傳統的動態單元匹配電路。第一級積分器使用了具有轉導增強的轉導電容式積分器，提供良好的線性度和低噪音性能。 此外，由於製程變異導致的電晶體不匹配和低頻雜訊的影響，這些原因會導致信號品質被影響並增加設計的困難，因此本設計使用斬 波器來緩解低頻雜訊以及電晶體不匹配的問題。此外在回授迴路中加入數位濾波器有助於減輕因使用斬波器而導致的量化噪音混疊的問題，且在不犧牲系統線性度的情況可以使用較少振盪器級數。 該晶片採用TSMC 180-nm CMOS製程。本讀取電路在10kHz頻寬下達到83.61dB的訊噪及失真比和84.06dB的動態範圍，功耗為83.64W（類比電壓1.8V，數位電壓1.2V），該晶片的面積為0.775mm2。且此電路的品質因素達到164.4dB。

This dissertation presents a second-order capacitively-coupled continuous-time delta-sigma modulator (CTDSM) based on a Gm-C integrator and voltage-controlled oscillator (VCO) for closed-loop neural recording sensor readout. This approach eliminates the need for a low-noise IA and an ADC in the front end. Instead, a high-resolution DSM serves as the entire sensing front-end. By utilizing the voltage-controlled oscillator in the second stage as a quantizer, the digital output, after dynamic element matching, enhances the digital-to-analog converter's linearity. This obviates the need for conventional dynamic element matching circuits. The first-stage integrator employs a Gm-C integrator with Gm-boosting, providing excellent linearity and low noise performance. Furthermore, because DC offset and flicker noise fall within the low-frequency range, signal quality is compromised, raising design complexity. This work uses a chopper to tackle these issues. Additionally, incorporating a FIR filter in the feedback loop helps mitigate the issue of quantization noise aliasing caused by the use of a chopper, and allows for the use of fewer oscillator stages without sacrificing system linearity. The chip is fabricated in the TSMC 0.18-μm CMOS process. The prototype readout circuit achieves 83.61dB SNDR in 10kHz bandwidth and 84.06dB dynamic range, consuming 83.64W (VDDA = 1.8, VDDD = 1.2) and 0.775mm2 active area. The sensor readout achieves FoMs of 164.4dB.