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  1. NTU Theses and Dissertations Repository
  2. 重點科技研究學院
  3. 積體電路設計與自動化學位學程
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93465
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dc.contributor.advisor郭斯彥zh_TW
dc.contributor.advisorSy-Yen Kuoen
dc.contributor.author施墨然zh_TW
dc.contributor.authorMo-Ran Shihen
dc.date.accessioned2024-08-01T16:16:10Z-
dc.date.available2024-08-02-
dc.date.copyright2024-08-01-
dc.date.issued2024-
dc.date.submitted2024-07-30-
dc.identifier.citation[1] R. Agarwal and S. D. Stoller. Run-time detection of potential deadlocks for pro- grams with locks, semaphores, and condition variables. In Proceedings of the 2006 workshop on Parallel and distributed systems: testing and debugging, pages 51–60, 2006.
[2] S. Bethu, P. Srikanth, and M. A. Ahmed. Contention management policy in soft- ware transactional memory in parallel and distributed systems. In 2014 Fourth International Conference on Communication Systems and Network Technologies, pages 357–361. IEEE, 2014.
[3] T. Crolard. A verified abstract machine for functional coroutines. arXiv preprint arXiv:1606.06376, 2016.
[4] P. Di Sanzo. Analysis, classification and comparison of scheduling techniques for software transactional memories. IEEE Transactions on Parallel and Distributed Systems, 28(12):3356–3373, 2017.
[5] A. Dragojevic and R. Guerraoui. Predicting the scalability of an stm: A pragmatic approach. In 5th ACM SIGPLAN Workshop on Transactional Computing, 2010.
[6] D. Engler and K. Ashcraft. Racerx: Effective, static detection of race conditions and deadlocks. ACM SIGOPS operating systems review, 37(5):237–252, 2003.
[7] P. Felber, C. Fetzer, P. Marlier, and T. Riegel. Time-based software transactional memory. IEEE Transactions on Parallel and Distributed Systems, 21(12):1793– 1807, 2010.
[8] J. Gray and L. Lamport. Consensus on transaction commit. ACM Transactions on Database Systems (TODS), 31(1):133–160, 2006.
[9] R. Guerraoui, M. Herlihy, M. Kapalka, and B. Pochon. Robust contention man- agement in software transactional memory. In Proceedings of the OOPSLA 2005 Workshop on Synchronization and Concurrency in Object-Oriented Languages (SCOOL’05), 2005.
[10] T. Heber, D. Hendler, and A. Suissa. On the impact of serializing contention management on stm performance. Journal of Parallel and Distributed Computing, 72(6):739–750, 2012.
[11] A. L. D. Moura and R. Ierusalimschy. Revisiting coroutines. ACM Transactions on Programming Languages and Systems (TOPLAS), 31(2):1–31, 2009.
[12] W. N. Scherer III and M. L. Scott. Advanced contention management for dynamic software transactional memory. In Proceedings of the twenty-fourth annual ACM symposium on Principles of distributed computing, pages 240–248, 2005.
[13] N. Shavit and D. Touitou. Software transactional memory. In Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing, pages 204–213, 1995.
[14] M. F. Spear, L. Dalessandro, V. J. Marathe, and M. L. Scott. A comprehen- sive strategy for contention management in software transactional memory. In Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, pages 141–150, 2009.
[15] M.A.Suleman,O.Mutlu,M.K.Qureshi,andY.N.Patt.Acceleratingcriticalsection execution with asymmetric multi-core architectures. ACM SIGARCH Computer Architecture News, 37(1):253–264, 2009.
[16] Tabassum and Meenu. Transactional memory: A review. In 2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS), pages 370–375, 2020.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93465-
dc.description.abstract本研究探討以協程 (coroutine) 實現軟體事務性記憶體 (Software Transactional Memory) 的運算排程,透過在協程間切換來提升其運算效能及可擴展性,軟體事務性記憶體用於處理協調衝突的方法,能夠大致區分為兩種架構:專注於衝突解決的衝突管理器 (Contention Manager) 或者是專注於衝突避免的排程器 (scheduler), 衝突管理器根據衝突解決策略決定衝突的事務 (transaction) 該中止或繼續執行,而排程器則透過排程來防止衝突再次發生,然而兩者都對可擴展性造成了極大的限制,許多文獻探討的機制將導致執行緒進行無謂的閒置,或者進行無效工作最終被中止,從而低效地利用計算資源。
本文提出了一種新穎的計算框架,稱為切換性軟體事務性記憶體 (switch-STM),將任務封裝為協程進行計算。當發生衝突時,切換協程以繼續計算,防止執行緒不必要地閒置。該框架不受任務排程限制,並具有高度的可擴展性。此外,它與衝突管理器兼容,可同時使用進一步提升計算效率。本文提出了三種協程切換策略,通過探索這些切換策略,推進軟體事務性記憶體計算框架的可擴展性和性能。
zh_TW
dc.description.abstractThis study explores the computational scheduling of Software Transactional Memory (STM) using coroutines, aiming to enhance its computational efficiency and scalability by switching between coroutines. Methods employed by STM to handle coordination conflicts can be broadly classified into two architectures: the Contention Manager, which focuses on conflict resolution, and the Scheduler, which focuses on conflict avoidance. While Contention Manager determines whether conflicting transactions should proceed or halt based on conflict resolution policies, Scheduler prevents conflicts from reoccurring by scheduling. However, both architectures impose significant limitations on scalability. Many existing mechanisms result in thread idleness or futile work that will ultimately be terminated, thereby inefficiently utilizing computational resources.
This paper proposes a novel computational framework called Switchable Software Transactional Memory (SwitchSTM), which encapsulates tasks into coroutines for compu- tation. When conflicts arise, coroutines are switched to continue computation, preventing unnecessary thread idling. This framework is not constrained by task scheduling limita- tions and exhibits high scalability. Additionally, it is compatible with Contention Man- ager, further enhancing computational efficiency. Three coroutine-switching strategies are proposed in the paper, advancing the scalability and performance of STM computational frameworks through the exploration of these switching strategies.
en
dc.description.provenanceSubmitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-08-01T16:16:10Z
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dc.description.provenanceMade available in DSpace on 2024-08-01T16:16:10Z (GMT). No. of bitstreams: 0en
dc.description.tableofcontentsAcknowledgements i
摘要 iii
Abstract v
Contents vii
List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
Chapter 2 Background 5
2.1 Parallel computing 5
2.2 Software Transactional Memory 7
2.3 TinySTM 10
Chapter 3 Performance Improvement 11
3.1 Conflict 11
3.2 Contention manager 14
3.3 Scheduler 17
3.4 Scalability Issue 19
Chapter 4 Coroutine 21
4.1 Concepts of coroutine 21
4.2 Symmetric Coroutine vs. Asymmetric Coroutine 23
4.3 Libaco 24
Chapter 5 SwitchSTM 27
5.1 Task Iterative STM 27
5.1.1 Task Iterative STM system architecture 27
5.1.2 Task Iterative STM Interaction 30
5.2 Core design of SwitchSTM 31
5.2.1 SwitchSTM system architecture 31
5.2.2 Transaction switching execution 33
5.2.3 Switcher implementation 35
5.2.4 Correctness of switching 38
Chapter 6 Evaluation 39
6.1 Configuration 39
6.2 Performance comparison with basic STM 40
6.3 Performance comparison with prior work 42
6.4 Abort ratio comparison with prior work 43
Chapter 7 Conclusion 45
Chapter 8 Future Work 47
References 49
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dc.language.isoen-
dc.subject運算架構zh_TW
dc.subject事務性記憶體zh_TW
dc.subject平行編程zh_TW
dc.subject平行運算zh_TW
dc.subject排程zh_TW
dc.subjectschedulingen
dc.subjectParallel Computingen
dc.subjectParallel Programmingen
dc.subjectcomputing architectureen
dc.subjecttransnational memoryen
dc.title以協程架構實現切換性軟體事務性記憶體的效能提升zh_TW
dc.titleEnhancing Performance of Switchable Software Transactional Memory through Coroutine Architecture Implementationen
dc.typeThesis-
dc.date.schoolyear112-2-
dc.description.degree碩士-
dc.contributor.oralexamcommittee林宗男;雷欽隆;袁世一;呂學坤zh_TW
dc.contributor.oralexamcommitteeTsungnan Lin;Chin-Laung Lei;Shih-Yu Yuan;Shyue-Kung Luen
dc.subject.keyword事務性記憶體,運算架構,排程,平行運算,平行編程,zh_TW
dc.subject.keywordtransnational memory,computing architecture,scheduling,Parallel Computing,Parallel Programming,en
dc.relation.page51-
dc.identifier.doi10.6342/NTU202401498-
dc.rights.note同意授權(全球公開)-
dc.date.accepted2024-08-01-
dc.contributor.author-college重點科技研究學院-
dc.contributor.author-dept積體電路設計與自動化學位學程-
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