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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93340| 標題: | 時間敏感網絡中的時序分析與優化 Timing Analysis and Optimization in Time-Sensitive Networking |
| 作者: | 王仲琦 Chung-Chi Wang |
| 指導教授: | 林忠緯 Chung-Wei Lin |
| 關鍵字: | 網路排程,時間敏感網路,非同步流量整形,QoS服務品質, Traffic Scheduling,Time Sensitive Networking,Asynchronous Traffic Shaping,Quality-of-Service,Simulated Annealing, |
| 出版年 : | 2024 |
| 學位: | 碩士 |
| 摘要: | 時間敏感網絡(TSN)是由IEEE 802.1時間敏感網絡任務組制定的一套標準,它增強了以太網網絡的功能,以滿足實時應用的要求。其基本概念是實現實時通信,確保有界的低延遲、高可靠性和精確的定時。IEEE 802.1Qbv標準定義了時間感知調整器(TAS)機制,該機制通過根據閘控列表開啟和關閉閘口來調度流量。在時間敏感網絡中,流的延遲不僅受其個別調度的影響,還受其他流的交互和其相應隊列的優先級的影響。因此,在優化過程中需要考慮流與隊列之間的映射。在這項工作中,我們專注於配置閘控列表和流到隊列的映射,以最小化在IEEE 802.1Qbv標準下的隊列延遲。我們提出了一種針對時間敏感網絡場景的時間分析方法,其中包括同步和異步流,以及它們的混合組合。我們通過使用模擬退火方法進行結果分析並尋找最優解。我們還提出了在模擬退火過程中增加找到可行解的概率的方法,以及更好的鄰近解選擇策略。結果表明,初始時將閘控列表的所有位設置為1可以顯著增加找到可行解的概率。此外,在模擬退火過程中在調整閘控列表之前分階段進行映射可以更有效地導致更好的解。 Time-Sensitive Networking (TSN) is a set of standards formulated by IEEE 802.1 Time-Sensitive Networking Task Group, which enhances the functions of Ethernet networks to meet the requirements of real-time applications. The basic concept is to enable real-time communication and ensure bounded low latency, high reliability, and precise timing. The IEEE 802.1Qbv standard defines the Time-Aware Shaper (TAS) mechanism, which schedules traffic by opening and closing the gate according to the Gate-Control List (GCL). In TSN, the latency of flows is influenced not only by their individual scheduling but also by the interactions with other flows and the priority of their respective queues. Therefore, the mapping between flows and queues is a crucial factor that needs to be considered during optimization. In this work, we focus on configuring the gate control list and mapping between flows and queues to minimize the queueing latency under the standard of IEEE 802.1Qbv. We propose a timing analysis method for TSN scenarios, which includes synchronous and asynchronous flows, as well as their hybrid combinations. We conduct an analysis of the results and seek the optimal solution using the SA (Simulated Annealing) method. We also propose methods to increase the probability of finding a feasible solution during the SA process, along with better neighbor solution selection strategies. The results indicate that initializing all bits of the GCL to 1 at the beginning can significantly increase the probability of finding a feasible solution. Additionally, performing mapping in stages before adjusting the GCL during the SA process can more efficiently lead to better solutions. |
| URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93340 |
| DOI: | 10.6342/NTU202401726 |
| 全文授權: | 同意授權(全球公開) |
| 顯示於系所單位: | 資訊工程學系 |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-112-2.pdf | 4.24 MB | Adobe PDF | 檢視/開啟 |
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