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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93029完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 許凱翔 | zh_TW |
| dc.contributor.author | Kai-Xiang Hsu | en |
| dc.date.accessioned | 2024-07-12T16:21:13Z | - |
| dc.date.available | 2024-07-13 | - |
| dc.date.copyright | 2024-07-12 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-07-11 | - |
| dc.identifier.citation | [1] B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge, first ed., 2020.
[2] G. R. Gangasani and P. R. Kinget, “A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS,”IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, pp. 803–807, May 2019. [3] Z. Zhang, G. Zhu, and C. P. Yue, “A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM,” IEEE J. Solid-State Circuits,vol. 55, pp. 1665–1683, June 2020. [4] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723–1732, Nov. 1996. [5] J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, pp. 1795–1803, Nov. 2003. [6] W. Jung, H. Choi, C. Jeong, K. Kim, W. Kim, H. Jeon, G. Koo, J. Kim, J. Seo, M. Ko,and J. Kim in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, title=A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter, year=2007, pages=310-605, doi=10.1109/ISSCC.2007.373418,month=Feb.,. [7] Z. Zhang, J. Yang, L. Liu, P. Feng, J. Liu, and N. Wu, “A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 26, pp. 933–944, May 2018. [8] E. Charbon, F. Sebastiano, M. Babaie, A. Vladimirescu, M. Shahmohammadi, R. B.Staszewski, H. A. R. Homulle, B. Patra, J. P. G. van Dijk, R. M. Incandela, L. Song,and B. Valizadehpasha, “15.5 Cryo-CMOS circuits and systems for scalable quantum computing,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 264–265, Feb 2017. [9] J. Gong, E. Charbon, F. Sebastiano, and M. Babaie, “A Cryo-CMOS PLL for Quantum Computing Applications,” IEEE J. Solid-State Circuits, vol. 58, pp. 1362–1375,May 2023. [10] M. Ferriss, A. Rylyakov, J. A. Tierno, H. Ainspan, and D. J. Friedman, “A 28 GHz Hybrid PLL in 32 nm SOI CMOS,” IEEE J. Solid-State Circuits, vol. 49, pp. 1027–1035, Apr 2014. [11] D. Kim and S. Cho, “A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, pp. 232–236,Feb 2019. [12] Z. Zhang and N. Wu, “Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (Invited Paper),” in IEEE Int. Conf.Solid-State Integr. Circuit Technol. (ICSICT), pp. 1–4, Nov 2020. [13] N. Mishra, L. M. Dani, K. Sanvaniya, S. Dasgupta, S. Chakraborty, and A. Bulusu,“Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 67, pp. 2352–2356, Nov. 2020. [14] N. Pourmousavian, F.-W. Kuo, T. Siriburanon, M. Babaie, and R. B. Staszewski,“A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 53, pp. 2572–2583, Sep. 2018. [15] M. Lee, S. Kim, H.-J. Park, and J.-Y. Sim, “A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC,” IEEE J. Solid-State Circuits, vol. 54, pp. 99–108, Jan. 2019. [16] H. R. Kooshkaki and P. P. Mercier in IEEE Custom Integrated Circuits Conf.(CICC), title=A 0.55mW Fractional-N PLL with a DC-DC Powered Class-D VCO Achieving Better than -66dBc Fractional and Reference Spurs for NB-IoT,year=2020, pages=1-4, doi=10.1109/CICC48029.2020.9075944, month=March,. [17] Z. Zhang, G. Zhu, and C. P. Yue, “A 0.25–0.4-V, Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps,”IEEE J. Solid-State Circuits, vol. 56, pp. 1871–1885, June 2021. [18] X. Xu, Z. Wan, W. Rhee, and Z. Wang, “A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation,” IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 68, pp. 3611–3620, Sep. 2021. [19] L. Feng, Q. Liao, W. Rhee, and Z. Wang in IEEE Asian Solid-State Circuits Conf.(A-SSCC), title=A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector, year=2023, pages=1-3, doi=10.1109/A-SSCC58667.2023.10347998, month=Nov.,. [20] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, pp. 117–121, Feb. 2009. [21] K. M. Megawer, A. Elkholy, D. Coombs, M. G. Ahmed, A. Elmallah, and P. K.Hanumolu, “A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC),pp. 392–394, Feb. 2018. [22] W. Bae, “Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures,” IEEE Access, vol. 10, pp. 80680–80694, 2022. [23] E. Vardarli, A. Mukherjee, X. Jin, P. Sakalas, and M. Schröter, “X- and Ku-Band SiGe-HBT Voltage-Controlled Ring Oscillators for Cryogenic Applications,” IEEE J. Explor. Solid-State Comput. Devices Circuits, vol. 7, pp. 209–217, Dec. 2021 | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93029 | - |
| dc.description.abstract | 本論文介紹了一種設計用於高頻率操作並保持低供應電壓的鎖相迴路（PLL）。此PLL採用雙通道架構，其中比例路徑保持迴路穩定，而積分路徑處理由溫度改變引起的環振盪器頻率變化。採用一個簡單的電路專門用於實現頻寬跟蹤功能。所有偏置電壓均由內部生成，以確保偏置水平完全由操作條件決定。
此PLL採用40納米TSMC CMOS技術實現，佔用核心面積為0.0054 mm2。它能夠在 4 到 353.15 K（-269.15 到 80 攝氏度）的寬廣溫度範圍內有效運行。在室溫下，基於10GHz輸出和0.6V供應電壓，此PLL表現出0.28 mW/GHz的功率效率。此外，對於0.6V供應電壓配置，它實現了低於-220dB的穩定品質因數（FoM）。 | zh_TW |
| dc.description.abstract | This thesis introduces a phase-locked loop (PLL) designed to operate at high frequencies while maintaining a low supply voltage. The PLL employs a dual-path architecture: the proportional path maintains loop dynamics, and the integral path compensates for frequency variations in the ring oscillator due to temperature fluctuations. A simple circuit is solely responsible for implementing the bandwidth tracking function. The biases are all generated internally, ensuring that the operating conditions alone determine the bias levels.
The proposed PLL, implemented in 40-nm TSMC CMOS technology, covers a core area of 0.0054 mm2. It operates effectively across a wide temperature range, from 4 K to 353.15 K (-269.15 to 80 oC). The PLL achieves a power efficiency of 0.28 mW/GHz, with a 10-GHz output and a 0.6V supply voltage at room temperature. Furthermore, it achieves a stable figure-of-merit (FoM) lower than -220 dB for the 0.6V supply voltage configuration. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-12T16:21:13Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-07-12T16:21:13Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書i
誌謝ii 摘要iii Abstract iv Contents v List of Figures viii List of Tables xi 1 Introduction 1 1.1 Motivation and Research Goals . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Basic Concepts 5 2.1 PLL Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Integer-N PLLs analysis [1] . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Phase domain Linear Model . . . . . . . . . . . . . . . . . . . . 8 2.3 Phase Noise and Jitters . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.2 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 Dual-path PLLs Concept . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Ring VCO free-running frequency . . . . . . . . . . . . . . . . . . . . . 16 2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 System Architecture and Building Blocks 21 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Proposed A 2.8mW 10-GHz Low-Voltage Ring-based PLL with Self-biased Bandwidth Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.2 Transfer function of a dual-path structure . . . . . . . . . . . . . 23 3.3 Ring Oscillator Topology . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 Negative Skew Oscillator . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 Characteristic of Ring VCO . . . . . . . . . . . . . . . . . . . . 25 3.4 Bandwidth tracking concept . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.1 Case I : Constant current ICP _P . . . . . . . . . . . . . . . . . . 30 3.4.2 Case II : Constant ratio FBW /FREF . . . . . . . . . . . . . . . . 31 3.5 Bandwidth tracking implementation . . . . . . . . . . . . . . . . . . . . 31 3.5.1 Case I : Constant current ICP _P . . . . . . . . . . . . . . . . . . 32 3.5.2 Case II : Constant ratio FBW /FREF . . . . . . . . . . . . . . . . 34 3.6 Other block implementation . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.1 Dynamic Charge Pump in I-path (IDCP) . . . . . . . . . . . . . . 34 3.6.2 Divider (DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.3 Phase Frequency Detector (PFD) in I-path . . . . . . . . . . . . . 36 3.6.4 Circuit for measurement . . . . . . . . . . . . . . . . . . . . . . 37 3.7 Noise analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 Measurement Result 41 4.1 Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 Common Temperature range (-60 to 80◦ C) . . . . . . . . . . . . . . . . 42 4.2.1 Measurement Environment . . . . . . . . . . . . . . . . . . . . . 42 4.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.3 Comparison and Performance Summary . . . . . . . . . . . . . . 49 4.3 Ultra Low Temperature (4K) . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.1 Probe station . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.2 Cryogenic Fridge . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 Conclusion 58 5.1 Thesis Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Bibliography 59 | - |
| dc.language.iso | en | - |
| dc.subject | 負斜率振盪器 | zh_TW |
| dc.subject | 雙迴路鎖相迴路 | zh_TW |
| dc.subject | 頻寬追蹤 | zh_TW |
| dc.subject | 量子運算 | zh_TW |
| dc.subject | 低溫 CMOS | zh_TW |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | Quantum computing | en |
| dc.subject | cryo-CMOS | en |
| dc.subject | Bandwidth-tracking | en |
| dc.subject | Negative-skew oscillator | en |
| dc.subject | Dual-Path PLL | en |
| dc.subject | Phase-Locked Loop（PLL） | en |
| dc.title | 應用於4-350K環境且具有頻寬追蹤之低功耗基於環形架構的鎖相迴路 | zh_TW |
| dc.title | A 4-350K Low-Power Ring-based Phase-Locked Loop with Bandwidth Tracking | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;林宗賢;張順志 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tsung-Hsien Lin;Soon-Jyh Chang | en |
| dc.subject.keyword | 鎖相迴路,雙迴路鎖相迴路,負斜率振盪器,頻寬追蹤,量子運算,低溫 CMOS, | zh_TW |
| dc.subject.keyword | Phase-Locked Loop（PLL）,Dual-Path PLL,Negative-skew oscillator,Bandwidth-tracking,Quantum computing,cryo-CMOS, | en |
| dc.relation.page | 62 | - |
| dc.identifier.doi | 10.6342/NTU202401663 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-07-11 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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