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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | zh_TW |
dc.contributor.advisor | Jenn-Gwo Hwu | en |
dc.contributor.author | 羅雅云 | zh_TW |
dc.contributor.author | Ya-Yun Lo | en |
dc.date.accessioned | 2024-07-12T16:15:27Z | - |
dc.date.available | 2024-07-13 | - |
dc.date.copyright | 2024-07-12 | - |
dc.date.issued | 2024 | - |
dc.date.submitted | 2024-07-10 | - |
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V., Singhal, S., Singh, S., & Yadav, S., “Comparative Studies of Electrical Properties of MFS and MIS Capacitors for Non-Volatile Memory Applications.” 2020 International Conference on Electrical and Electronics Engineering (ICE3), pp. 131-135. DOI: 10.1109/ICE348803.2020.9122867 [16] Lin, J. Y., & Hwu, J. G., “Enhanced Transient Behavior in MIS(p) Tunnel Diodes by Trench Forming at the Gate Edge.” IEEE Transactions on Electron Devices, vol. 68, Issue: 9, pp. 4189-4194, Sep. 2021. DOI: 10.1109/TED.2021.3095052. [17] Huang, S. W., & Hwu, J. G., “Improved Two States Characteristics in MIS Tunnel Diodes by Oxide Local Thinning Enhanced Transient Current Behavior.” IEEE Transactions on Electron Devices, vol. 69, Issue: 12, pp. 7107-7112, Dec. 2022. DOI: 10.1109/TED.2022.3215103. [18] Huang, S. W., & Hwu, J. G., “Capacitance Analysis of Transient Behavior Improved Metal-Insulator-Semiconductor Tunnel Diodes With Ultra Thin Metal Surrounded Gate.” IEEE Journal of the Electron Devices Society, vol. 9, pp. 1041-1048, 2021. DOI: 10.1109/JEDS.2021.3123332. [19] Chen, B. J. (2020). Study of Edge-Etched Al2O3 Dielectric as Multi-Level Charge Storage Region in an Edge-Sensing Coupled MIS(p) TD. Unpublished Master Thesis, National Taiwan University, Taipei, Taiwan. [20] Lin, J. C. (2022). Study of Nonvolatile Memory in Coupled MIS(p) TD with Anodization-Compensated Al2O3 Dielectric. Unpublished Master Thesis, National Taiwan University, Taipei, Taiwan. [21] Yim, K., Yong, Y., Lee, J., Lee, K., Nahm, H.-H., Yoo, J., Lee, C., Seong Hwang, C., & Han, S., “Novel high-κ dielectrics for next-generation electronic devices screened by automated ab initio calculations.” NPG Asia Materials, vol. 7, Issue: 6, p. e190, 2015. DOI: 10.1038/am.2015.57. [22] Kingon, A. I., Maria, J.-P., & Streiffer, S. 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G., “Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors.” IEEE Transactions on Electron Devices, vol.61, Issue: 10, pp. 3562-3565, Oct. 2014. DOI: 10.1109/TED.2014.2346238. [27] Meliolla, G., Surawijaya, A., Sulthoni, M. A., & Adiono, T., “Study of tunneling gate oxide and floating gate thickness variation effects to the performance of split gate flash memory.” 2017 International Symposium on Electronics and Smart Devices (ISESD), pp. 256-259. DOI: 10.1109/ISESD.2017.8253343. [28] Válik, L., Ťapajna, M., Gucmann, F., Fedor, J., Šiffalovič, P., & Fröhlich, K., “Distribution of fixed oxide charge in MOS structures with ALD grown Al2O3 studied by capacitance measurements.” The Ninth International Conference on Advanced Semiconductor Devices and Mircosystems, pp.227-230, 2012. DOI: 10.1109/ASDAM.2012.6418526. [29] Shamala, K. S., Murthy, L. C. S., & Narasimha Rao, K., “Studies on optical and dielectric properties of Al2O3 thin films prepared by electron beam evaporation and spray pyrolysis method.” Materials Science and Engineering: B, vol. 106, Issue: 3, pp. 269-274, 2004. DOI: 10.1016/j.mseb.2003.09.036. [30] Winter, R., Ahn, J., McIntyre, P. C., & Eizenberg, M., “New method for determining flat-band voltage in high mobility semiconductors.” Journal of Vacuum Science & Technology B, vol. 31, Issue: 3, p. 030604, 2013. DOI: 10.1116/1.4802478. [31] Hsu, T. H., & Hwu, J. G., “Prolonged Transient Behavior of Ultrathin Oxide MIS-Tunneling Diode Induced by Deep Depletion of Surrounded Coupling Electrode.” IEEE Transactions on Electron Devices, vol. 67, Issue: 8, pp. 3411-3416, Aug. 2020. DOI: 10.1109/TED.2020.2998099. [32] Cheng, C.-F., Yang, Y.-C., & Hwu, J.-G., “Effect of Oxide Thickness on The Two-State Characteristics in MIS(p) Tunnel Diode with Ultrathin Metal Surrounded Gate.” ECS Journal of Solid State Science and Technology, vol. 8, Issue: 12, p. N214, 2019. DOI: 10.1149/2.0191912jss. [33] Huang, S. W., & Hwu, J. G., “Transient Current Enhancement in MIS Tunnel Diodes With Lateral Electric Field Induced by Designed High-Low Oxide Layers.” IEEE Transactions on Electron Devices, vol. 68, Issue: 12, pp. 6580-6585, Dec. 2021. DOI: 10.1109/TED.2021.3122814. [34] Minki, C., Maitra, K., & Mukhopadhyay, S., “Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits.” 2008 IEEE Custom Integrated Circuits Conference, pp. 285-288. DOI: 10.1109/CICC.2008.4672077. [35] Raut, P., Nanda, U., Panda, D. K., & Nguyen, H. P. T., “Performance Analysis of Double Gate Junctionless TFET with respect to different high-k materials and oxide thickness.” 2022 2nd International Conference on Artificial Intelligence and Signal Processing (AISP), pp.1-5. DOI: 10.1109/AISP53593.2022.9760584. [36] Pei, Y., Yin, C., Kojima, T., Bea, J. C., Kino, H., Fukushima, T., Tanaka, T., & Koyanagi, M., “MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and HfO2 High-k Blocking Dielectric.” IEEE Transactions on Nanotechnology, vol. 10, Issue: 3, pp. 528-531. DOI: 10.1109/TNANO.2010.2050331. [37] El-Atab, N., Nayfeh, A., Turgut, B. B., & Okyay, A. K., “MOS memory with double-layer high-κ tunnel oxide Al2O3/HfO2 and ZnO charge trapping layer.” 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), pp. 766-768. DOI: 10.1109/NANO.2015.7388722. [38] Lin, Y. H., Li, J. H., You, H. C., Hong, J. S., Tsai, W. T., & Chen, H. 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[42] Mativenga, M., Haque, F., Billah, M. M., & Um, J. G., “Origin of light instability in amorphous IGZO thin-film transistors and its suppression.” Scientific Reports, vol. 11, Issue: 1, p. 14618, 2021. DOI: 10.1038/s41598-021-94078-8. | - |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/93009 | - |
dc.description.abstract | 本篇論文主要在探討高介電常數材料對金氧半電容元件的基本電特性及記憶體應用中電荷儲存性能之影響。有別於傳統平面金氧半穿隧二極體,我們在氧化矽上堆疊兩層高介電材料氧化鋁,形成一具高介電氧化物之金氧半電容元件。在這個元件中,氧化鋁層扮演電荷捕捉及儲存材料的角色,實現此元件多位階電荷記憶特性之應用。在加入高介電材料層之後,金氧半元件的性質和行為會產生許多變化。在電性方面,因為絕緣層整體厚度增加,電流級距因穿隧機率下降而變小,進而導致位移電流的效應變得更加明顯。此外,在相反電壓掃描方向的電容-電壓特性量測中,此元件呈現了兩個不同的平帶電壓值,展現其在表現元件內部不同電荷儲存情況的能力。因此,我們在元件上施加特定時間的電壓作為記憶體寫入資料的過程,並再次測量電容-電壓特性以記錄平帶電壓的變化,用以代表不同的讀取資料。而透過調整施加電壓的大小和持續時間,我們可以達到此元件多位階電荷儲存的目的。接著,我們深入探討此高介電材料金氧半元件中的暫態行為。根據元件在施加電壓之後讀取的暫態電流特性,我們可以推測其內部載子間的互動和流動方向。在施加正負電壓之後,會形成不同大小及方向的電流,利用此不同暫態行為的表現也可以作為記憶資料的應用。此外,元件在施加電壓之後電容數值會維持一段時間,也展現了其記憶資料的持續能力。而作為對照組,我們也做了一具有約十奈米厚氧化矽的金氧半元件,並探討其暫態行為。透過二維TCAD模擬工具的輔助,我們探討在施加電壓之後此元件內部電子和電洞濃度,以及載子之間復合速率隨時間的變化,來與在實驗量測中所發現的電流峰值做對照,並驗證其中載子移動與彼此互動的機制。另一方面,我們將高介電金氧半元件做金屬後退火之處理,並作相似的電性量測,探討退火消除元件內部缺陷與氧化層電荷的能力,以及此元件在退火處理之後,其記憶資料表現與暫態行為的變化。最後,經由元件製程與退火處理優化來達到具高穩定性,且特性理想的非揮發記憶體金氧半元件。 | zh_TW |
dc.description.abstract | This thesis delved into the impact of high-k dielectric layers on the fundamental electrical characteristics and charge storage performance in metal-oxide-semiconductor (MIS) devices for memory applications. Different from a conventional planar MIS tunnel diode (TD) device, we stacked two layers of high-k material, Al2O3, on SiO2. The Al2O3 layers played the role of charge trapping material in this device, enabling the realization of multi-level memory states. There are various changes in the behaviors of MIS device after the introduction of high-k dielectric layers. In the aspect of changes in electrical characteristics, the current order decreased due to the thickening of insulator layers, thereby causing the effect of displacement current became more significant. Moreover, the C-V characteristics have shown distinct flat-band voltage values for opposite voltage sweeping directions, indicating the potential for representing charge storage conditions in high-k MIS. Therefore, we stressed voltage pulses as the writing data process, then reading the C-V properties again to record the variations in flat-band voltage values. Through the adjustment of pulse magnitude and pulse duration, we could obtain multiple charge storage states in this device. Furthermore, the transient behaviors in high-k MIS were investigated. For memory applications, voltage pulses were also applied on the device, then switched to a reading gate bias to read the transient current. Depending on the movement of carriers, we achieved current values with different magnitudes and directions, creating a current window for data recording. The C-t measurement exhibited that the capacitance values persisted for a certain duration of measurement, indicating the retention ability of data in this device. In addition, the transient properties of MIS device with pure thick SiO2 were explored. 2D TCAD simulation investigated the concentration of electron and hole, as well as the recombination rate in silicon substrate after negative voltage pulsing. This analysis clarified the I-t properties and interaction between carriers in this device. On the other hand, we subjected the high-k MIS to post-metallization-annealing (PMA), followed by similar measurements, including memory window performance and transient behaviors investigation. Since PMA would repair the defects and oxide charges in dielectric layers, reducing the quantity of traps in the device, the distinction of flat-band voltage window and current window decreased. Nonetheless, the high-k MIS retained its capacity for utilization in memory applications. Moreover, PMA improved the ideality of electrical characteristics and the stability of device structure, providing a potential and promising process for non-volatile memory device. | en |
dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-07-12T16:15:27Z No. of bitstreams: 0 | en |
dc.description.provenance | Made available in DSpace on 2024-07-12T16:15:27Z (GMT). No. of bitstreams: 0 | en |
dc.description.tableofcontents | 誌謝 i
摘要 ii Abstract iii Contents v Figure Captions viii Table Captions xiii Chapter 1 Introduction 1 1-1 Motivation 1 1-2 The Growth Mechanisms of Dielectric Layers 4 1-2-1 Silicon Oxide by Anodic Oxidation 5 1-2-2 Aluminum Oxide by Evaporation Deposition and Anodic Oxidation 6 1-3 Evaluation of Oxide Thickness by Electrical Characteristics of MIS Devices 7 1-4 The Memory Mechanisms in MIS Device with High-k Dielectric 10 1-5 Summary 12 Chapter 2 Electrical Characteristics and Memory Performances of MIS Device with High-k Dielectric Layers 19 2-1 Introduction 19 2-2 Experimental 20 2-3 Results and Discussion 23 2-3-1 The Basic Electrical Characteristics of MIS Devices 23 2-3-2 Memory Mechanisms in MIS with Al2O3/SiO2 Stacking Structure 28 2-3-3 Memory Window Performances by Voltage Pulsing Treatments 29 2-4 Summary 32 Chapter 3 The Retention of Memory States and Transient Behaviors in MIS Devices 47 3-1 Introduction 47 3-2 Experimental 49 3-3 Results and Discussion 50 3-3-1 The C-t Characteristics and Performance of Memory States Retention in MIS Device with High-k Dielectric 50 3-3-2 The Current Transient Behaviors in MIS Device with High-k Dielectric 52 3-3-3 Investigation and Simulation of I-t Characteristics in MIS with Pure SiO2 55 3-4 Summary 57 Chapter 4 Conclusion 73 4-1 Conclusion 73 4-2 Suggestions for Future Work 75 4-2-1 Thickness and Dielectric Constant Effect of High-k Dielectrics on Memory Performance and Tansient Behaviors in MIS Device 75 4-2-2 The Enhancement of Memory Window in MIS Device Via Light Illumination 77 Reference 80 | - |
dc.language.iso | en | - |
dc.title | 具高介電常數氧化鋁與氧化矽堆疊結構金氧半元件多位階電荷儲存及暫態記憶特性之研究 | zh_TW |
dc.title | Study of Multiple Charge-Storage States and Transient Memory Behaviors in MIS(p) with High-k Al2O3/SiO2 Stacking Structure | en |
dc.type | Thesis | - |
dc.date.schoolyear | 112-2 | - |
dc.description.degree | 碩士 | - |
dc.contributor.oralexamcommittee | 林浩雄;陳弈君 | zh_TW |
dc.contributor.oralexamcommittee | Hao-Hsiung Lin;I-Chun Cheng | en |
dc.subject.keyword | 高介電常數材料堆疊結構,金氧半電容元件,多位階電荷儲存,平帶電壓,暫態行為,金屬後退火, | zh_TW |
dc.subject.keyword | high dielectric constant (high-k) material stacking structure,metal-insulator-semiconductor (MIS) capacitor,multi-level charge-storage states,flat-band voltages,transient behaviors,post-metallization-annealing (PMA), | en |
dc.relation.page | 88 | - |
dc.identifier.doi | 10.6342/NTU202401606 | - |
dc.rights.note | 同意授權(全球公開) | - |
dc.date.accepted | 2024-07-10 | - |
dc.contributor.author-college | 電機資訊學院 | - |
dc.contributor.author-dept | 電子工程學研究所 | - |
顯示於系所單位: | 電子工程學研究所 |
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