應用於5G毫米波之注入鎖定倍頻器與基於SiP技術透過選擇不同輸出阻抗轉換達成最佳化之超寬頻平衡功率放大器

Abstract

本論文主要探討射頻積體電路設計與射頻積體電路在異質整合技術中的應用。分為三個部分。 第一部分探討隨著第五代移動通信的發展，對更高數據傳輸速率的需求不斷增加。這需要更大的頻寬和更快的傳輸速率。倍頻器顯著提高時脈訊號的工作頻率，降低TRX系統設計的複雜性。我們提出兩個單級LC-注入鎖定六倍頻器（ILFS），採用90nm CMOS製程實現，並描述了ILFS的電路設計、工作原理和測量結果。該ILFS電路為差動輸入和單端輸出，由一次諧波注入鎖定振盪器（ILO）、三倍頻器和push-push倍頻器組成。第一個ILFS使用八角形電感。其自身震盪頻率約為41.52 GHz，0 dBm的輸入功率下DC功耗為9.03 mW，並且在0 dBm輸入功率下的輸出鎖定範圍為10.21％。第二個ILFS使用8字形電感以減少電磁干擾生成。自震頻率約為37.2 GHz，其DC功耗為7.72 mW，並且在0 dBm輸入功率下的輸出鎖定範圍為17.4％。該部分還對設計的電感的射頻性能進一步分析和比較。模擬顯示了被干擾者和干擾者之間的基板雜訊耦合和距離間的雜訊耦合，8字形電感顯著減少耦合效應。通過測量結果，可以明顯看出8字形電感ILFS的性能優於八角形電感ILFS [10]。 第二部分提出了兩種基於覆晶系統封裝（SiP）技術與電子設計自動化的超寬頻（UWB）平衡功率放大器。對於系統晶片（SoC），常用方法是將所有子電路積體設計到單一製程。然而，在射頻電路中，採用SoC方法需要複雜的匹配設計，導致開發成本增加。在本研究中，採用SiGe製程，設計兩種單元功率放大器實現平坦的S21響應，並且使用更簡單的輸入/輸出匹配設計。第一類單元功率放大器採用並聯結構。隨後，第二類單元功率放大器的設計建立在第一類的基礎上，唯一的差異在於兩並聯疊接架構的元件尺寸，主要目標是增強與第一類相比的增益和輸出功率。此外，這第二類單元功率放大器，與正交混合器結合使用，選擇了最佳的阻抗匹配值，以保持整個UWB範圍內增益的平坦度。此外，通過使用WIPD製程（WIN Integrated Passive Device Technology）製造的正交混合器來改善這兩種單元功率放大器的S11、S22的性能不佳。因此，使用覆晶封裝技術可以有效降低由於主動電路中複雜匹配設計而導致的增加的晶圓製造成本。此外，本文提出的優化阻抗匹配方法可以與SiP技術結合，形成改進的平衡功率放大器系統。這種增強的系統具有為UWB功率放大器設計提供實際新應用的潛力 [11]。 最後一部分是根據第一部分去做改良。提出了一種針對放大倍頻器信號的電流重複利用倍頻器-達林頓放大器（FD-DA），由post-layout simulation 觀察出其 harmonic rejection 與輸出功率大幅改善。 harmonic rejection 改善21.2 dB , 訊號放大達到16.5dB , 總功率消耗為 11.86mW [12].

This thesis primarily explores Radio Frequency Integrated Circuits (RFIC) and their application in heterogeneous integration technologies. It is divided into three sections. The first section addresses the growing demand for higher data transmission rates in line with the development of 5th generation mobile communications. This necessitates increased bandwidth and faster transmission rates. Frequency multipliers significantly enhance clock signal operating frequencies and notably reduce the complexity in TRX system design. We proposed two single-stage LC-tank injection-locked frequency sixtuplers (ILFSs) fabricated in a 90 nm CMOS process and it describes the circuit design, operation principle, and measurement results of the ILFSs. The ILFS circuit with a differential input and single-phase output is made of a first-harmonic injection-locked oscillator (ILO), a frequency tripler, and a push-push doubler. The first ILFS uses an octagonal inductor. The free-running frequency is around 41.52 GHz, DC power consumption is 9.03 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 10.21 %. The second ILFS uses an 8-shaped inductor for low electromagnetic (EM) noise generation. The free-running frequency is around 37.2 GHz, DC power consumption is 7.72 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 17.4 %. This section also provides a further analysis and comparison of the RF performance of on-chip inductors designed. Simulation shows the substrate noise coupling and distance noise coupling between victim and aggressor, the 8-shaped inductor exhibits a significant reduction in coupling. By the measurement results, it is evident that the performance of the 8-shaped inductor ILFS is superior to that of the octagonal inductor ILFS [10]. The second section proposes two improved ultra-wideband (UWB) balanced power amplifiers based on the flip-chip system-in-package (SiP) technique and electronic design automation (EDA). The conventional approach for system-on-chip (SoC) involves integrating all sub-circuits designs into a single manufacturing process. However, in radio frequency circuits, adopting the SoC approach necessitates intricate matching designs, leading to an increase in development costs. In this study, two types of SiGe unit power amplifiers attempted to achieve flat S21 response using simpler matching for input/output. The cascode architecture was adopted as the main structure for the first type of unit power amplifier. Subsequently, the design of the second type unit power amplifier was built upon the foundation of the first type, with the only difference being the device size of a two paralleled cascode structure, and the primary goal is to enhance both gain and output power compared to first type. Additionally, this second type unit power amplifier, in conjunction with a quadrature hybrid coupler, the optimal impedance matching value was selected to maintain the flatness of gain across the entire UWB range. Furthermore, The poor performance for S11,22 of these two types unit power amplifiers were improved by using quadrature hybrid couplers manufactured using the WIPD process (WIN Integrated Passive Device Technology). Therefore, using flip-chip packaging technology can effectively reduce the increased wafer fabrication costs caused by complex matching designs in active circuits. Besides, the method for optimizing impedance matching presented in this paper can be combined with SiP techniques to form an improved balanced power amplifier system. This enhanced system has the potential to offer a practical new application for UWB power amplifier design [11]. The final part involves improving based on the first part. A Current-Reuse Frequency Doubler-Darlington Amplifier (FD-DA) is proposed for amplifying frequency multiplier signals. Post-layout simulation reveals significant improvements in harmonic rejection and output power. The harmonic rejection improves by 21.2 dB, while the signal amplification reaches 16.5 dB. The total power consumption is 11.86 mW [12].