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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | zh_TW |
| dc.contributor.advisor | Tai-Cheng Lee | en |
| dc.contributor.author | 陳冠余 | zh_TW |
| dc.contributor.author | Guan-Yu Chen | en |
| dc.date.accessioned | 2024-04-10T16:13:31Z | - |
| dc.date.available | 2024-04-11 | - |
| dc.date.copyright | 2024-04-10 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-04-09 | - |
| dc.identifier.citation | [1] H.K. Jung, K. Lee, J.S. Kim, J.J. Lee, J.Y. Sim, and H.J. Park, “A 4 gb/s 3bit parallel transmitter with the crosstalkinduced jitter compensation using tx data timing control,” IEEE Journal of SolidState Circuits, vol. 44, no. 11, pp. 2891–2900, 2009.
[2] H.K. Jung, S.M. Lee, J.Y. Sim, and H.J. Park, “A slewrate controlled transmitter to compensate for the crosstalkinduced jitter of coupled microstrip lines,” in IEEE Custom Integrated Circuits Conference 2010, pp. 1–4, Sep. 2010. [3] S.Y. Kao and S.I. Liu, “A 7.5gb/ s onetapffe transmitter with adaptive farend crosstalk cancellation using duty cycle detection,” IEEE Journal of SolidState Circuits, vol. 48, pp. 391–404, Feb 2013. [4] B. Razavi, Design of Integrated Circuits for Optical Communications. Wiley Press, second ed., 2012. [5] J. Lee, Communication Integrated Circuits. [6] N. Holland, Interfacing Between LVPECL, VML, CML, and LVDS Levels. TEXAS INSTRUMENTS, 2002. [7] M. Kossel, C. Menolfi, J. Weiss, P. Buchmann, G. von Bueren, L. Rodoni, T. Morf, T. Toifl, and M. Schmatz, “A tcoilenhanced 8.5 gb/s highswing sst transmitter in 65 nm bulk cmos with −16 db return loss over 10 ghz bandwidth,” IEEE Journal of SolidState Circuits, vol. 43, pp. 2905–2920, Dec 2008. [8] Y.S. Sohn, J.C. Lee, H.J. Park, and S.I. Cho, “Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board,” IEEE Transactions on Advanced Packaging, vol. 24, pp. 521–527, Nov 2001. [9] B. Razavi, Design of CMOS PhaseLocked Loops: From Circuit Level to Architecture Level. Cambridge Press, 2020. [10] Y. Lu, K. Jung, Y. Hidaka, and E. Alon, “Design and analysis of energyefficient reconfigurable preemphasis voltagemode transmitters,” IEEE Journal of SolidState Circuits, vol. 48, pp. 1898–1909, Aug 2013. [11] S. Saxena, R. K. Nandwana, and P. K. Hanumolu, “A 5 gb/s energyefficient voltagemode transmitter using timebased deemphasis,” IEEE Journal of SolidState Circuits, vol. 49, pp. 1827–1836, Aug 2014. [12] X. Gao, E. A. M. Klumperink, M. Bohsali, and B. Nauta, “A low noise subsampling pll in which divider noise is eliminated and pd/cp noise is not multiplied by n2,” IEEE Journal of SolidState Circuits, vol. 44, pp. 3253–3263, Dec 2009. [13] C. Fan, W.H. Yu, P.I. Mak, and R. P. Martins, “A 40gb/ s pam4 transmitter using a 0.16pj/ bit sstcmlhybrid (sch) output driver and a hybridpath 3tap ffe scheme in 28nm cmos,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, pp. 4850–4861, Dec 2019. [14] P.J. Peng, Y.T. Chen, C.H. Chen, S.T. Lai, H.E. Huang, H.H. Lu, and T.C. Yu, “A 50gb/ s quarterrate voltagemode transmitter with threetap ffe in 40nm cmos,” in ESSCIRC 2018 IEEE 44th European Solid State Circuits Conference (ESSCIRC), pp. 174–177, Sep. 2018. [15] Y. Chang, A. Manian, L. Kong, and B. Razavi, “An 80gb/ s 44mw wireline pam4 transmitter,” IEEE Journal of SolidState Circuits, vol. 53, pp. 2214–2226, Aug 2018. [16] J. W. P. William J. Dally, Digital Systems Engineering. Cambridge University Press, 1998. [17] J. Buckwalter and A. Hajimiri, “Cancellation of crosstalkinduced jitter,” IEEE Journal of SolidState Circuits, vol. 41, pp. 621–632, March 2006. [18] H.K. Jung, I.M. Yi, S.M. Lee, J.Y. Sim, and H.J. Park, “A transmitter to compensate for crosstalkinduced jitter by subtracting a rectangular crosstalk waveform from data signal during the data transition time in coupled microstrip lines,” IEEE Journal of SolidState Circuits, vol. 47, pp. 2068–2079, Sep. 2012. [19] H.G. Ko, S. Shin, J. Oh, K. Park, and D.K. Jeong, “6.7 an 8gb/s/μm ffecombined crosstalkcancellation scheme for hbm on silicon interposer with 3dstaggered channels,” in 2020 IEEE International SolidState Circuits Conference ( ISSCC), pp. 128–130, Feb 2020. [20] K. M. Tony Chan Carusone, David Johns, Analog Integrated Circuit Design. Wiley Press, second ed., 2011. [21] Virtuoso Parameterized Cell SKILL Reference. Cadence Design Systems, 2020. [22] Virtuoso Parameterized Cell Reference. Cadence Design Systems, 2021. [23] SKILL Development of Parameterized Cells Lecture Manual. Cadence Design Systems, 2004. [24] Cadence SKILL Language User Guide, Cadence Design Systems. Cadence Design Systems, 2021. [25] Virtuoso Relative Object Design SKILL Reference. Cadence Design Systems, 2020. [26] Component Description Format User Guide. Cadence Design Systems, 2011. [27] Cadence® Design Framework II SKILL Functions Reference. Cadence Design Systems, 2004. [28] Virtuoso Relative Object Design User Guide. Cadence Design Systems, 2020. [29] C. Aprile, A. Cevrero, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, L. Kull, I. Oezkaya, Y. Leblebici, V. Cevher, and T. Toifl, “An eightlane 7gb/ s/pin source synchronous singleended rx with equalization and farend crosstalk cancellation for backplane channels,” IEEE Journal of SolidState Circuits, vol. 53, pp. 861– 872, March 2018. [30] Y.U. Jeong, S. Choi, S. Kim, and J.H. Chae, “Singleended receiverside crosstalk cancellation with independent gain and timing control for minimum residual fext,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 4793– 4803, Dec 2023. [31] Q. Liu, L. Du, and Y. Du, “A 0.90tb/ s/in 1.29pj/ b wireline transceiver with singleended crosstalk cancellation coding scheme for highdensity interconnects," IEEE Journal of Solid-State Circuits, vol. 58, pp. 2326-2336, Aug 2023. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92549 | - |
| dc.description.abstract | 本論文介紹了一種單端傳輸機輸出級電路，該驅動器結合了前饋式等化器（feed-forward equalizer）和遠端串音干擾（far-end crosstalk）消除技術，所提出的傳輸機輸出級電路對靜態模式與偶模式信號應用不同強度的前饋式等化器，從而消除了兩條並聯微帶線之間串音所引起的串音干擾引起抖動（crosstalk induced jitter），同時保存奇模式信號固有的高頻補償特性以進一步補償通道損耗。在28 奈米CMOS 製程下，所實現之傳輸機晶片於8Gbps 的傳輸速度下可使峰對峰抖動（peak-to-peak jitter）和串音干擾引起抖動分別減少48 個（29 ps）和114 個百分比，並擴張眼圈之水平張開幅度（位容錯率小於1e12）34 個百分比。
在有線傳輸的應用中，鎖相迴路提供的時脈訊號品質將直接影響傳輸機的性能表現，而鎖相迴路中的振盪器往往需要大量的設計迭代來實現最佳效能。本論文同時介紹了一種數位控制振盪器之電路佈局產生器（digitally-controlled oscillator layout generator），來大幅降低電路佈局所需耗費的時間。藉由所開發之佈局產生器，設計者可以根據所設計的環狀振盪器之電晶體尺寸與級數及數位類比轉換器（digital-to-analog converter）之位元數，直接輸入設計參數於數位控制振盪器佈局產生器，來自動生成數位控制振盪器的電路佈局。因此，我們可以大大節省設計電路後所耗費在電路佈局上的時間，減少執行後模擬(post-simulation)流程所需要的時間成本，進而加速研發時間。 | zh_TW |
| dc.description.abstract | This thesis present a single-ended TX output driver, which combines a feed-forward equalizer (FFE) and a far-end crosstalk (FEXT) canceller. The proposed output driver eliminates the crosstalk induced jitter (CIJ) between two parallel coupled microstrip lines while preserving the inherent high-frequency boosting signal for channel loss compensation. Implemented in a 28nm CMOS technology, the driver reduces the peak-to-peak jitter and CIJ by 48% (29 ps) and 114%, respectively, at 8 Gb/s. Furthermore, it increases the horizontal eye-opening (BER <1E12) by 34%.
In wireline communication design, the quality of the clock signal from a phase-locked loop (PLL) directly impacts system performance. Nevertheless, the oscillators within the PLL often necessitate extensive design iterations to attain optimal performance. This thesis also introduces a layout generator for a digitally-controlled oscillator (DCO). With the DCO layout generator, designers can specify the MOS sizes, stages of the ring oscillator, and the number of bits of the digital-to-analog converter (DAC), and input these design parameters directly into the layout generator. This process automates the generation of circuit layouts for DCOs, resulting in substantial time savings in circuit layout design. Consequently, it diminishes the time cost associated with post-simulation and accelerates development time. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-04-10T16:13:31Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-04-10T16:13:31Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 誌謝iii
摘要iv Abstract v Contents vi List of Figures ix List of Tables xii 1 Introduction 1 1.1 Motivation and Research Goals . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Basic Concepts 3 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Wireline Communication Fundamentals . . . . . . . . . . . . . . . . . . 3 2.2.1 PseudoRandom Binary Sequence (PRBS) . . . . . . . . . . . . 3 2.2.2 InterSymbol Interference (ISI) . . . . . . . . . . . . . . . . . . 4 2.2.3 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.4 Reflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.5 Bit Error Rate (BER) . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 MultiLane Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.1 Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3.2 FeedForward Equalizer (FFE) . . . . . . . . . . . . . . . . . . . 9 2.3.3 Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 CIJ Compensation Concept 12 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 Timing Control Technique [1] . . . . . . . . . . . . . . . . . . . 12 3.2.2 Voltage Control Technique [2, 3] . . . . . . . . . . . . . . . . . . 14 3.3 Proposed Crosstalk Cancellation Approach . . . . . . . . . . . . . . . . 16 3.3.1 CIJ Compensation Principle . . . . . . . . . . . . . . . . . . . . 16 3.3.2 XTC Coefficient Determination . . . . . . . . . . . . . . . . . . 18 4 Circuit Implementation 20 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 Proposed TX Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 Mode Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 Mode Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 Layout Floor Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Measurement Result 27 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Crosstalk Channel Board . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 Chip Die Photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 Experimental Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 DigitallyControlled Oscillator (DCO) Layout Generator 36 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3 DCO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3.1 DigitallyControlled Interface . . . . . . . . . . . . . . . . . . . 37 6.3.2 Oscillator Architecture . . . . . . . . . . . . . . . . . . . . . . . 39 6.3.3 DigitallyControlled Oscillator . . . . . . . . . . . . . . . . . . . 39 6.4 Parameterized Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.4.1 What is a Parameterized Cell ? . . . . . . . . . . . . . . . . . . . 40 6.4.2 Relative Object Design . . . . . . . . . . . . . . . . . . . . . . . 41 6.5 Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.5.1 Fine DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.5.2 Coarse DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.5.3 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.5.4 DigitallyControlled Oscillator . . . . . . . . . . . . . . . . . . . 45 6.5.5 PostSimulation Result . . . . . . . . . . . . . . . . . . . . . . . 46 7 Conclusion 48 Bibliography 50 | - |
| dc.language.iso | en | - |
| dc.subject | 串音干擾引起抖動 | zh_TW |
| dc.subject | 遠端串音干擾消除 | zh_TW |
| dc.subject | 微帶線 | zh_TW |
| dc.subject | 有線通信 | zh_TW |
| dc.subject | 符號間干擾 | zh_TW |
| dc.subject | 數位控制振盪器 | zh_TW |
| dc.subject | 佈局產生器 | zh_TW |
| dc.subject | far-end crosstalk (FEXT) cancellation | en |
| dc.subject | layout generator | en |
| dc.subject | digitally-controlled oscillator | en |
| dc.subject | intersymbol interference (ISI) | en |
| dc.subject | wireline | en |
| dc.subject | microstrip | en |
| dc.subject | crosstalkinduced jitter (CIJ) | en |
| dc.title | 遠端串音干擾消除與前饋式等化器共同設計之8Gbps傳輸機輸出級電路/ 數位振盪器之電路佈局產生器 | zh_TW |
| dc.title | An 8 Gbps Far-End Crosstalk Cancellation and FFE Co-designed TX Output Driver / Digitally-Controlled Oscillator Layout Generator | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-2 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 劉深淵;林宗賢;陳筱青 | zh_TW |
| dc.contributor.oralexamcommittee | Shen-Iuan Liu;Tsung-Hsien Lin;Hsiao Chin Chen | en |
| dc.subject.keyword | 串音干擾引起抖動,遠端串音干擾消除,微帶線,有線通信,符號間干擾,數位控制振盪器,佈局產生器, | zh_TW |
| dc.subject.keyword | crosstalkinduced jitter (CIJ),far-end crosstalk (FEXT) cancellation,microstrip,wireline,intersymbol interference (ISI),digitally-controlled oscillator,layout generator, | en |
| dc.relation.page | 53 | - |
| dc.identifier.doi | 10.6342/NTU202400847 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2024-04-10 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| 顯示於系所單位： | 電子工程學研究所 | |
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