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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃鐘揚 | zh_TW |
| dc.contributor.advisor | Chung-Yang Huang | en |
| dc.contributor.author | 許祐綾 | zh_TW |
| dc.contributor.author | Yu-Ling Hsu | en |
| dc.date.accessioned | 2024-03-07T16:16:28Z | - |
| dc.date.available | 2024-03-08 | - |
| dc.date.copyright | 2024-03-07 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-02-18 | - |
| dc.identifier.citation | [1] Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, and Robert Brayton. Efficient computation of ECO patch functions. In Proceedings of the 55th Annual Design Automation Conference, DAC ’18, New York, NY, USA, 2018. Association for Computing Machinery.
[2] Michael Huth and Mark Ryan. Logic in Computer Science: Modelling and Reasoning about Systems. Cambridge university press, 2004. [3] Elliott Mendelson. Introduction to Mathematical Logic. CRC press, 2009. [4] Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, and Robert K Brayton. FRAIGs: A Unifying Representation for Logic Synthesis and Verification. Technical report, ERL Technical Report, 2005. [5] Robert K Brayton, Gary D Hachtel, Curt McMullen, and Alberto Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis, volume 2. Springer Science & Business Media, 1984. [6] Wikipedia. Unate function. https://en.wikipedia.org/wiki/Unate_function. Accessed: 2024-02-09. [7] Poul F. Williams, Armin Biere, Edmund M. Clarke, and Anubhav Gupta. Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking. In E. Allen Emerson and Aravinda Prasad Sistla, editors, Computer Aided Verification, pages 124–138, Berlin, Heidelberg, 2000. Springer Berlin Heidelberg. [8] Armin Biere, Marijn Heule, and Hans van Maaren. Handbook of satisfiability, volume 185. IOS press, 2009. [9] Niklas Een and Niklas Sörensson. An extensible sat-solver. In International conference on theory and applications of satisfiability testing, pages 502–518. Springer, 2003. [10] Niklas Sorensson and Niklas Een. Minisat v1. 13-a sat solver with conflict-clause minimization. SAT, 2005(53):1–2, 2005. [11] Raimund Ubar and Dominique Borrione. Design error diagnosis in digital circuits without error model. In VLSI: Systems on a Chip: IFIP TC10 WG10. 5 Tenth International Conference on Very Large Scale Integration (VLSI'99) December 1–4, 1999, Lisboa, Portugal, pages 281–292. Springer, 2000. [12] Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, and Jie-Hong Roland Jiang. A robust functional ECO engine by SAT proof minimization and interpolation techniques. In 2010 IEEE/ACM International Conference on Computer-Aided Design(ICCAD), pages 729–734, 2010. [13] Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, and Chung-Yang Huang. Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(3):467–478, 2013. [14] ICCAD CAD Contest 2017 Problem A. Resource-aware Patch Generation. https://iccad-contest.org/2017/CAD-contest-at-ICCAD2017/index.html. Accessed: 2024-01-27. [15] ICCAD CAD Contest 2021 Problem A. Functional ECO with Behavioral Change Guidance. https://iccad-contest.org/2021/Problems.html. Accessed:2024-01-27. [16] Alan Mishchenko. ABC: System for Sequential Logic Synthesis and Formal Verification. https://github.com/berkeley-abc/abc. Accessed: 2024-02-01. [17] Cadence Design Systems, Inc. Logical Equivalence Checking(LEC). License: Conformal_ECO_GXL 21.2. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92142 | - |
| dc.description.abstract | 這份研究提出了一種新的方法,以解決先前工程改變命令方法中觀察到的限制。 在給定一組候選校正點的情況下,先前的方法使用量化布林公式求解器來檢驗候選的校正點集合是否足以修復錯誤,但有兩個缺點:首先,往往候選校正點不足,從而導致在重試中的運行時間過長。 其次,候選集合中可能有些多餘的校正點,導致產生的補丁將遠離最佳解。 為此,我們提出了一種高效的全稱量詞消除的方法,從而可以將校正點識別問題轉為合取範式,並透過SAT求解器解決。 我們進一步利用產生的SAT證明來提取一組最小的校正點集合,以修正工程改變命令的錯誤。
透過將證明核心作為阻斷子句加入SAT求解器中,我們能夠列舉候選集合的所有可能解。 實驗結果表明,在效率和性能方面,與傳統策略和商業工具相比,本方法取得了改進。 | zh_TW |
| dc.description.abstract | This work introduces a novel method to address limitations observed in previous Engineering Change Order (ECO) approaches. Given a set of rectification candidates, previous methods use Quantified Boolean Formula (QBF) solver to verify whether the candidates are adequate to fix the bug. The deficiencies of the previous approaches are twofold: First, it is often that the sets of candidates are inadequate, thus leading to excessive runtime in retrying. Second. the identified rectification points may contain redundancies and therefore the resultant patch will be far from optimality. In response, the proposed method introduces an efficient elimination of universal quantifiers, and thus the rectification point identification problem can be modelled as Conjunctive Normal Form (CNF) and solved by an SAT solver. We further utilize the resulting SAT proof to extract a minimal set of rectification points to fix the ECO bug.
By adding proof cores as blocking clauses to the SAT solver, we are able to enumerate all the possible solutions of the candidate set. Experimental results demonstrate an improvement over conventional strategies and a commercial tool in terms of efficiency and performance. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-03-07T16:16:28Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-03-07T16:16:28Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | Acknowledgements i
中文摘要 iii Abstract iv Contents vi List of Figures ix List of Tables x Denotation xi Chapter 1 Introduction 1 1.1 Problem Statement and Motivation . . . . . . . . . . . . . . . . . . 1 1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2 Background Knowledge 4 2.1 De Morgan’s Laws in First-Order Logic . . . . . . . . . . . . . . . . 4 2.2 Functional Reduced And-Inverter Graph . . . . . . . . . . . . . . . . 5 2.3 Unate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Universal Quantifier Elimination of Direct Fanin Variable in Conjunctive Normal Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.5 SAT Problem and MiniSat . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 Error Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.7 Patch Function Computation . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Overview of the Rectification Point Qualification Algorithm 9 3.1 Formulation of the Rectification Point Qualification . . . . . . . . . 9 3.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Three Key Algorithmic Steps . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 Generate Rectification Point Candidates . . . . . . . . . . . . . . . 11 3.3.2 Quantifier Elimination and Auxiliary Variable Introduction . . . . . 12 3.3.3 UNSAT Core Extraction . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Assumption for the Problem Input . . . . . . . . . . . . . . . . . . . 13 Chapter 4 Algorithm for Picking Rectification Candidates 15 4.1 Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Suspicious Score Calculation . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Candidate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 5 Algorithm for Constructing Quantifier-Eliminated CNF with Auxiliary Variables 20 5.1 Universal Quantifier Elimination on Unate Gate in AIG Circuit . . . 21 5.2 Introduce Auxiliary Variable st . . . . . . . . . . . . . . . . . . . . 23 5.3 Fanout Consistency of a Gate . . . . . . . . . . . . . . . . . . . . . 24 Chapter 6 Robustness and Accuracy in Quantifier Elimination Procedure 28 6.1 Quantifier Elimination on F rather than Miter M . . . . . . . . . . . 28 6.2 The Number of Direct Fanouts of t . . . . . . . . . . . . . . . . . . 30 6.3 Handling Multiple POs . . . . . . . . . . . . . . . . . . . . . . . . . 31 Chapter 7 Algorithm for UNSAT Core Extraction 33 7.1 Decision of Universal Quantifier Activation . . . . . . . . . . . . . . 34 7.2 SAT Proof and Conflict Analysis . . . . . . . . . . . . . . . . . . . . 34 7.3 Iterative Search for Diverse Solution Sets . . . . . . . . . . . . . . . 35 Chapter 8 Experimental Results and Analysis 37 8.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1.1 Test Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1.2 Patch Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1.3 Patch Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.1.4 Comparative Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 38 8.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.2.1 Key Metrics Explanation . . . . . . . . . . . . . . . . . . . . . . . 39 8.2.2 Result Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 9 Conclusion and Future Directions 42 9.1 Strengths of Our Work . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 Limitations and Future Directions . . . . . . . . . . . . . . . . . . . 43 References 45 | - |
| dc.language.iso | en | - |
| dc.subject | 工程改變命令 | zh_TW |
| dc.subject | 可滿足性問題 | zh_TW |
| dc.subject | 校正點 | zh_TW |
| dc.subject | ECO | en |
| dc.subject | SAT | en |
| dc.subject | Rectification Point | en |
| dc.title | 利用可滿足性問題證明核心生成的合格校正點進行工程改變命令補丁優化 | zh_TW |
| dc.title | ECO Patch Optimization by Rectification Point Qualification with SAT Proofs | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 江介宏;黃紹倫 | zh_TW |
| dc.contributor.oralexamcommittee | Jie-Hong Roland Jiang;Shao-Lun Huang | en |
| dc.subject.keyword | 工程改變命令,校正點,可滿足性問題, | zh_TW |
| dc.subject.keyword | ECO,Rectification Point,SAT, | en |
| dc.relation.page | 47 | - |
| dc.identifier.doi | 10.6342/NTU202400668 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-02-18 | - |
| dc.contributor.author-college | 電機資訊學院 | - |
| dc.contributor.author-dept | 電子工程學研究所 | - |
| dc.date.embargo-lift | 2029-02-14 | - |
| 顯示於系所單位: | 電子工程學研究所 | |
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