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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 方煒 | zh_TW |
| dc.contributor.advisor | Wei Fang | en |
| dc.contributor.author | 邵長威 | zh_TW |
| dc.contributor.author | Chang-Wei Shao | en |
| dc.date.accessioned | 2024-03-05T16:15:54Z | - |
| dc.date.available | 2024-03-06 | - |
| dc.date.copyright | 2024-03-05 | - |
| dc.date.issued | 2024 | - |
| dc.date.submitted | 2024-02-16 | - |
| dc.identifier.citation | Albert Chun Chen Liu, Oscar Ming Kin Law. Jul 2020. Deep Learning-Hardware Design, 3-2 to 3-8. Chuan Hwa Book Co., LTD.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/92095 | - |
| dc.description.abstract | 由於深度卷積神經網路 (DCNN) 在人工智慧 (AI) 的應用中對計算力的需求指數成長，對於專用硬體的架構設計來說是一大挑戰。小型系統的功能支援上通常不齊全，而大型晶片變得過於複雜。在不同功能的運算上，同樣仰賴太多模組的切換，導致過多資料搬移，有高延遲與部分模組使用率不高的問題。
這項研究提出了一種基於統計方法的改進結構，包括參數分析、演算法劃分後映射到硬體，以在暫存器傳輸級 (RTL) 建構出一個管線的硬體架構。 研究結果顯示，本論文的架構在單核處理元件 (PE) 上比起其他評比 (e.g, MIT Eyeriss, UCLA DCNN Acc., Google TPU) 的設計，有較佳的硬體重用率、硬體共用性且支援最多功能，也減少了激活函數時的延遲，並確保了所有功能的運算都在核心內完成，且擁有相同的週波時間。 | zh_TW |
| dc.description.abstract | The demand for computing power in deep convolutional neural networks (DCNNs) for artificial intelligence (AI) applications is exponentially increasing. Designing application-specific hardware architectures poses significant challenges. Smaller systems typically lack essential functionality, while large-scale chips become overly complex. Dynamic switching of modules with different functions results in excessive data movement, leading to high latency and underutilization of certain modules.
This research proposes a statistical-based improved structure comprising parameter analysis, algorithm partitioning, and hardware mapping to construct a pipeline-based architecture in Register Transfer Level (RTL). The research results indicate that this architecture demonstrates improved hardware reuse, sharing, and functionality on a single processing element (PE) compared to the benchmark. (e.g, MIT Eyeriss, UCLA DCNN Acc., Google TPU). It reduces activation function latency and ensures that all functions operate in-core with consistent cycle times. | en |
| dc.description.provenance | Submitted by admin ntu (admin@lib.ntu.edu.tw) on 2024-03-05T16:15:54Z No. of bitstreams: 0 | en |
| dc.description.provenance | Made available in DSpace on 2024-03-05T16:15:54Z (GMT). No. of bitstreams: 0 | en |
| dc.description.tableofcontents | 口試委員會審定書 i
Acknowledgements ii 中文摘要 iv Abstract v List of Figures viii List of Tables x Chapter 1 Introduction 1 1.1 Background 1 1.2 Research Scope 3 1.3 Research Objectives 4 1.4 Contributions of This Research 6 Chapter 2 Related Work 9 2.1 Exploration of AI and CNN Domains 9 2.2 Comparison of CPU, GPU, ASIC, FPGA in CNN 10 2.3 Optimizing ASIC Architectures in AI Computation 12 2.4 Benchmarks for Deep Learning Accelerator 16 Chapter 3 Research Method and Design 17 3.1 Research Gap 17 3.2 Deep Learning Accelerator Architecture Design Flow 17 3.3 Popular DCNN Models Analysis 19 3.4 Layers Parameters Statistics 25 3.5 Function and Specification Definition 26 3.6 Algorithm Design and Segmentation 30 3.7 Divide-and-conquer 35 3.8 System Flow Design 38 3.9 Instruction Set Design 41 Chapter 4 Implementation 45 4.1 Architecture Mapping to RTL 45 Chapter 5 Results and Discussion 49 5.1 Operations Cycle Time Analysis 49 5.2 Performance Analysis and Simulation 55 5.3 Data Reuse Rate 55 5.4 Design Comparison 57 5.5 Data Path Comparison 60 5.6 Benchmark 63 Chapter 6 Conclusions and Future Work 67 6.1 Pros and Cons 67 6.2 Research Contributions 69 6.3 Research Limitations 69 6.4 Future Work 70 Reference 73 | - |
| dc.language.iso | en | - |
| dc.title | 卷積神經網路之深度學習加速器架構設計 | zh_TW |
| dc.title | Architecture Design of Deep Learning Accelerator for CNN | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 112-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 陳倩瑜;曾國師 | zh_TW |
| dc.contributor.oralexamcommittee | Chien-yu Chen;Kuo-Shih Tseng | en |
| dc.subject.keyword | 計算機架構,深度學習加速器,深度卷積神經網路,人工智慧,演算法, | zh_TW |
| dc.subject.keyword | Computer Architecture,Deep Learning Accelerator (DLA),Deep Convolutional Neural Networks (DCNN),Artificial Intelligence (AI),Algorithms, | en |
| dc.relation.page | 79 | - |
| dc.identifier.doi | 10.6342/NTU202400510 | - |
| dc.rights.note | 同意授權(全球公開) | - |
| dc.date.accepted | 2024-02-17 | - |
| dc.contributor.author-college | 生物資源暨農學院 | - |
| dc.contributor.author-dept | 生物機電工程學系 | - |
| 顯示於系所單位： | 生物機電工程學系 | |
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