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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9183
標題: | 晶片網路下之權重式錯誤偵測及架構 Weighted Error Detection Method and NoC Architecture |
作者: | Chung-Huang Jiang 江忠桓 |
指導教授: | 賴飛羆 |
關鍵字: | 晶片網路,容錯,錯誤偵測, network on chip,NoC,fault tolerant,error detection, |
出版年 : | 2009 |
學位: | 碩士 |
摘要: | 單晶片系統(System-on-Chip)設計目前已經廣泛地運用在多媒體、電信通訊、消費性電子領域的電路設計。隨著製程不斷地縮小,越多的矽智財(IP)可以整合到單一晶片裡。各個矽智財之間的訊息交換將變成系統效能的瓶頸。一個基於封包交換傳輸方式的晶片網路(Network-on-chip)被提出來克服解決系統晶片連結的問題。在現今的晶片網路設計中服務品質(QoS)成為一個主要的設計目標,其中容錯性為服務品質中的一個部分。在之前的所設計過的錯誤偵測方法以及架構中在功率消耗以及延遲上並不符合需求。在此篇論文中,我們提出一個具權重式的錯誤偵測以及架構來達成可容錯性。設計主旨為將較具關鍵性及重要性的資料封包部分,以較嚴密的方式檢查之;剩下的部分,用較簡單的方式檢查之。實驗結果顯示,在大部分的情況下,我們所提出的方式及架構,會有較佳的'功耗延遲”的乘積。 System-on-chip design has been commonly used in modern circuit design in multimedia, telecommunications and consumer electronics domain. With the technology scaled down, more IP cores can be integrated into a single ship. The interconnection between IP becomes the performance bottleneck. Network-on-chip (NoC) which is packet switch based communication is proposed to overcome the SoC interconnection problem. In modern NoC design, QoS (quality of service) becomes the main issue. Fault tolerant is one part of QoS. In fact, the previous error mechanism and architecture in fault tolerant NoC design can not meet our demands, no matter power or latency. In this thesis, we proposed a weighted error detection and architecture to overcome fault tolerant issue. The concept is letting the significant and critical part be checked strictly and the other part will be checked slightly. Simulation and results demonstrate that it can reduce the latency power product better than previous architectures in most conditions. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/9183 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 資訊工程學系 |
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ntu-98-1.pdf | 1.06 MB | Adobe PDF | 檢視/開啟 |
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