鉍背閘極電晶體製作與特性研究

Abstract

本論文研究以Bi/SiO2 /p+ Si(100)為結構的鉍通道背閘極電晶體的製程與電晶體特性。在製程方面，我們使用分子束磊晶(Molecular Beam Epitaxy, MBE)在二氧化矽基板上成長鉍薄膜，透過EBSD、XRD和SEM觀察鉍薄膜的晶粒尺寸、晶格排列及表面形態，接著經由黃光微影製作出背閘極電晶體。最後我們量測了電晶體的電性，並比較其在真空環境下熱退火後的電性差異。 在熱退火的研究中，我們發現熱退火可以改善鉍與接觸金屬間的歐姆接觸，使接觸電阻下降。而最佳的熱退火條件是溫度150°C、時間6小時，在這個條件下，熱退火對鉍薄膜的表面形態變化較小。 在鉍通道背閘極的電性研究中，我們使用鉍的厚度為30 nm，鉍的性質仍呈現半金屬特性，電晶體無法關閉。然而我們對量測到的Id-Vg曲線，利用微分的方式，求得電晶體的轉導，並計算場效載子遷移率(field effect mobility)。 不同電晶體的場效遷移率有很大的變化範圍，最低值小於1 cm2 /Vs ，最高值可達325 cm2 /Vs。最高值略高於現有文獻中的最高值235 cm2 /Vs 。我們以EBSD、XRD和SEM觀察鉍薄膜，發現場效遷移率越高的電晶體，有越大的晶粒尺寸和越高的XRD峰值。除此之外，我們也發現能透過提高電晶體的汲極偏壓，使電流變化量及場效遷移率提升，並提出能帶模型來對此現象進行解釋。

This paper investigate the process and transistor characteristics of a bismuth channel back-gated transistor with a structure of Bi/SiO2/p+ Si(100). In the process, we use Molecular Beam Epitaxy (MBE) to grow bismuth thin films on SiO2. The grain size, lattice arrangement, and surface morphology of the bismuth film are observed through EBSD, XRD, and SEM. Subsequently, back-gated transistors are fabricated using photolithography. Finally, we measure the transistor's electrical properties and compare the after annealing in a vacuum environment. In the annealing study, we find that annealing improves the ohmic contact between bismuth and the contact metal, leading to a decrease in contact resistance. The optimal annealing conditions are a temperature of 150°C for 6 hours. Under these conditions, the thermal annealing leads to a relatively minor change in the surface morphology of the bismuth film. In the study of the bismuth back-gated transistor, we use a bismuth thickness of 30 nm, and despite the semi-metallic nature of bismuth, the transistor cannot be turned off. However, by analyzing the measured Id-Vg curves, we obtain the transconductance of the transistor and calculate the field-effect mobility. The field effect mobility of different transistors varies widely, with a minimum value of less than 1 cm2/Vs and maximum value of 325 cm2/Vs. The highest value is higher than the highest value of *235 cm2/Vs reported in existing literature [1]. Through EBSD, XRD, we find that transistors with higher field effect mobility have larger grain sizes and higher XRD peak values. Additionally, we discover that increasing the drain bias of the transistor can enhance the change in current and field-effect mobility, proposing a model to explain this phenomenon.