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標題: | 離子佈植隔離技術應用於低溫金氧半與量子元件 Ion Implant Isolation for Cryo-CMOS and Quantum Devices |
作者: | 廖宸嶢 Chen-Yao Liao |
指導教授: | 李峻霣 Jiun-Yun Li |
關鍵字: | 量子點,量子霍爾效應,庫倫阻斷,離子佈植隔離,低溫, Quantum Dot,Quantum Hall Effect,Coulomb Blockade,Ion-Implant Isolation,Cryogenic, |
出版年 : | 2024 |
學位: | 碩士 |
摘要: | 由於較長的相干時間與VLSI相容性,量子點是一個可依靠作為量子運算的平台。本論文中,分別於非摻雜式矽/矽鍺與鍺/鍺矽,實現量子霍爾效應與庫倫阻斷等量子傳輸現象。另外,由於量子點製程複雜,為減少閘極層數,離子佈植隔離技術被提出,並以金氧半場效電晶體作為測試平台。
非摻雜式矽/矽鍺的傳輸現象以電子密度與遷移率為表徵討論,且觀察到整數與分數量子霍爾效應。對於非摻雜式鍺/鍺矽而言,以一手指式量子點量測傳輸現象與庫倫阻斷。庫倫阻斷的巔峰之間距離較理論值大二個數量級,其中原因可能為較小的等效量子點面積。 透過離子佈植,量子點的閘極數得以減少。離子佈植定義電晶體以離子佈植而非閘極定義通道區域。對於矽金氧半場效電晶體而言,4 K量測結果顯示離子佈植區域絕緣。低溫下,即使離子佈植區域上方有閘極,仍未有載子被引誘出。這些結果顯示金氧半場效電晶體的通道區域可以被離子佈植定義,也因此,離子佈植未來有被應用於減低量子點複雜度的潛力。 Semiconductor quantum dots (QDs) are a promising platform for quantum computing due to the long coherence time and VLSI compatibility. In this thesis, quantum transport properties, such as quantum Hall effect and Coulomb blockade, in undoped Si/SiGe and Ge/GeSi heterostructures are investigated. In addition, since the device fabrication of QDs requires complicated processing steps, to reduce the number of gate layers, ion implant isolation is proposed and characterized using MOSFETs as a test platform. The transport properties of undoped Si/SiGe are characterized by the electron density and mobility. Both integer and fractional quantum Hall effect are observed. For the undoped Ge/GeSi heterostructure, a finger-like quantum dot is characterized by both gate control test and Coulomb blockade measurement. The distance between Coulomb peaks is two orders larger than the theoretical one, which might be attributed to smaller effective quantum dot size. The number of the gates used for QDs can be reduced by using an implant step to create amorphous layers for electrical isolation. Implant-isolated MOSFETs are investigated by using the implant step to define the channel areas rather than the top gate. For Si MOSFETs, measurement results at 4 K show that the implanted regions are electrically insulating. Even there exist gates on top of the implanted region, there is no carrier induced at cryogenic temperatures. These results suggest that the channel area of MOSFETs can be defined by ion implantation, and this ion-implant isolation technique has great potential for reducing the complexity of QD fabrication in the future. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/91682 |
DOI: | 10.6342/NTU202400357 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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ntu-112-1.pdf | 4.99 MB | Adobe PDF | 檢視/開啟 |
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